欢迎访问ic37.com |
会员登录 免费注册
发布采购

MAS3509F 参数 Datasheet PDF下载

MAS3509F图片预览
型号: MAS3509F
PDF下载: 下载PDF文件 查看货源
内容描述: MAS 35x9F MPEG 2/3层, AAC音频解码器, G.729附录编解码器 [MAS 35x9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec]
分类和应用: 解码器编解码器
文件页数/大小: 92 页 / 1187 K
品牌: MICRONAS [ MICRONAS ]
 浏览型号MAS3509F的Datasheet PDF文件第13页浏览型号MAS3509F的Datasheet PDF文件第14页浏览型号MAS3509F的Datasheet PDF文件第15页浏览型号MAS3509F的Datasheet PDF文件第16页浏览型号MAS3509F的Datasheet PDF文件第18页浏览型号MAS3509F的Datasheet PDF文件第19页浏览型号MAS3509F的Datasheet PDF文件第20页浏览型号MAS3509F的Datasheet PDF文件第21页  
DATA SHEET  
MAS 35x9F  
2.10.MP3 Block Input Mode  
Table 2–3: MP3 bit rate vs. number of interrupts  
A new so-called MP3 block input mode is now avail-  
able which improves the input timing behavior of the  
MAS 35x9F MPEG 1/2/2.5 Layer 3 decoder. The fol-  
lowing sections provide a detailed description of this  
new mode.  
Bit Rate  
[kbit/s]  
Number of Interrupts  
[1/s]  
20  
16  
14  
12  
10  
8
320  
256  
224  
192  
160  
128  
112  
96  
2.10.1.Functional Description of the MP3 Block  
Input Mode  
In MP3 block input, the MAS 35x9F generates a  
demand for new input data each time one of its two  
input buffers becomes available. The controller then  
has to send one block of input data via the serial inter-  
face SDIB. The block size is 2048 byte. The demand is  
signalized via a pulse on the EOD pin.  
7
Fig. 2–13 shows that the number of interrupts per sec-  
ond does not depend on the data rate at the serial  
interface. The maximum input data bit clock rate sup-  
ported by the MAS 35x9F for all MPEG audio sampling  
rates is 1.4 MHz.  
6
80  
5
64  
4
Table 2–3 shows the average number of interrupts per  
second for several typical MP3 bit rates.  
The time period between two interrupts may vary  
slightly even for fixed bit rate input streams due to the  
MP3 specific bit reservoir.  
Interrupt  
Interrupt  
a) SIC  
b) SIC  
Data blocks in a) and b) contain the same number of bytes.  
t
Data block a) is sent with a lower data rate than data block b).  
Fig. 2–13: Data Block Timing Diagram  
Micronas  
June 30, 2004; 6251-505-1DS  
17