HAL855
DATA SHEET
3.6.1. Specification of Biphase-M Output
Definition of Biphase-M Pulses
In case of output format Biphase-M, a continuous data
stream is provided. It consists of:
A logical “0” is coded as no output level change within
the bit time. A logical “1” is coded as an output level
change between 50% and 80% of the bit time. After
each bit, an output level change occurs.
– 1 SYNC bit defining the bit time tp0,
– 14 data bits (DAT)
– 1 parity bit (DP)
Data Bits (DAT)
– a gap (signal quiescent) of 8 x tp0
The 12 MSB of the 14 data bits (DAT) contain the digi-
tal output reading.
The complete signal period is T = 24 x tp0.
The signal quiescent level and the polarity of the
SYNC bit is shown in Fig. 3–5.
Data Parity Bit (DP)
This parity bit is “1” if the number of zeros within the 14
data bits is even. The parity bit is “0” if the number of
zeros is odd.
Type
SYNC Bit Polarity
HAL855
negative
Note: If the part number output is activated the part
number will be transmitted 2 times after
power-up (see also (see Fig. 4–6 on page 31).
The first Biphase-M protocol respectively the
first PWM period after power-up is not valid.
HAL855:
SYNC BIT
DAT
DP
V
OUT
8 x t
p0
Fig. 3–5: Output format Biphase-M: continuous data stream
24
Nov. 26, 2008; DSH000149_003EN
Micronas
MICRONAS [ MICRONAS ]
