CIP 3250A
ADVANCE INFORMATION
2
Table 2–10: I C-Bus operation, continued
Sub-
Address
(decimal)
Label
Bit No.
(LSB = 0)
Typical
Operation
Value
Function
2
I C registers for SYNCHRONIZATION
17
NEGCLK
5
0
1
select active clockedge for inputs and outputs
0 =allinputsandoutputsrelatetorisingedgeatCLKinput(DIGIT3000)
1=allinputsandoutputsrelatetofallingedgeatCLKinput(DIGIT2000)
17
SYNCSIM
0
HSYNC, VSYNC input
0 = FSY-/SKEW-protocol (see <17>D2KSYNC)
1 = HSYNC at FSY-pin, VSYNC at AVI-pin
(see also <07>FSYINV, <10>AVIINV)
17
D2KSYNC
1
0
sync protocol at FSY-pin
0 = DIGIT 3000 (FSY protocol)
AVI-Pin and FSY-Pin with trigger level at 1.2 Volt
1 = DIGIT 2000 (SKEW protocol)
AVI-Pin and FSY-Pin with Schmitt-Trigger characteristic
10
07
AVIINV
6
7
0
0
polarity of AVI signal
0 = vertical sync at falling edge of AVI (if <17>SYNCSIM = 1
1 = vertical sync at rising edge of AVI (if <17>SYNCSIM = 1)
FSYINV
polarity of FSY signal (see also <17>SYNCSIM)
0 = horizontal sync at falling edge of FSY (if <17>SYNCSIM = 1)
select always <07>FSYINV = 0 if <17>SYNCSIM = 0
1 = horizontal sync at rising edge of FSY (if <17>SYNCSIM = 1)
17
17
17
SYNCIN
7
6
2
0
0
0
UV (chroma) multiplex control of digital YUVin
0 = by AVI (active video in)
1 = by 72 bit data (DIGIT 2000)
SYNCOUT
P72BEN
UV (chroma) multiplex control of YUV output
0 = by AVO (active video out)
1 = by 72 bit data (DIGIT 2000)
72 bit data and clock bypass enable
0 = off
1 = on (DIGIT 2000)
H-sync
(see Fig. 2–13)
<21>DL2*2 + 2 clocks
48..212 clocks
DL2-WR
D2KSYNC SYNCSIM
delay
<17>
<17>
(clocks)
AVI
X
1
4
DL2-RD
1
0
0
0
15
23
4 clocks <10>DL1ON = 0
82 clocks <10>DL1ON = 1
24 clocks
102 clocks
H-sync delay in respect to falling edge of FSY/
SKEW (H-sync is derived from FSY/SKEW)
Fig. 2–14: DL2-setup (<17>PXSKWON = 1)
FSY
H-sync
DL2-WR
DL2-RD
(delay/clocks see table)
AVO
program delay
see <21>DL2
<23>AVHSTRT + 11 – <22>AVPR clocks
DL2-reset
Fig. 2–15: DL2-reset during line 7
(<17>PXSKWON = 0)
Fig. 2–13: H-sync reference generation
26
Micronas
MICRONAS [ MICRONAS ]
