CIP 3250A
ADVANCE INFORMATION
3.3. Pin Descriptions
Pin 29 – AVI Active Video Input (Fig. 3–5)
In a DIGIT 2000 application, this input can be connected
to ground. In a DIGIT 3000 application, this input ex-
pects the DIGIT 3000 AVI signal. In a stand alone ap-
plication, this input expects the VSYNC vertical sync
pulse. Connect to ground if not used.
Pin 1 – STANDBY Input (Fig. 3–2)
Via this input pin, the standby mode of the CIP 3250A is
enabled. A high level voltage switches all outputs to tris-
tate mode, and power consumption is significantly re-
duced. When the IC is returned to active mode, a reset
is generated internally. Connect to VSS if not used.
Pin 30 – FSY Front Sync Input (Fig. 3–5)
In a DIGIT 2000 application, this input pin expects the
DIGIT 2000 SKEW protocol. In a DIGIT 3000 applica-
tion, this input expects the DIGIT 3000 FSY protocol. In
a stand alone application, this input expects the HSYNC
horizontal sync pulse. Connect to ground if not used.
Pins 2 to 9 – B7 to B0 Blue Output (Fig.3–3 )
In a stand alone application, where the CIP 3250A
servesasanA/D-converter, thesearetheoutputsforthe
digital Blue signal (pure binary) or the digital U signal (2’s
complement). Leave vacant if not used.
2
Pins 31 to 32 – SDA and SCL of I C-Bus (Fig. 3–6)
2
These pins connect to the I C bus, which takes over the
control of the CIP 3250A via the internal registers. The
SDA pin is the data input/output, and the SCL pin is the
clock input/output of I C bus control interface. All regis-
Pins 10 to 17 – GL7 to GL0 Green/Luma Output
(Fig.3–3 )
2
At these outputs, the digital luminance signal is received
in pure binary coded format for DIGIT 2000 and DIGIT
3000 applications. In a stand alone application, where
the CIP 3250A serves as an A/D-converter, these are
the outputs for the digital Green signal (pure binary) or
the digital luma signal (pure binary). Leave vacant if not
used.
ters are writeable (except address hex27) and readable.
Pins 33 to 35 – PRIO0 to PRIO2 Priority Bus (Fig. 3–7)
These pins connect to the Priority Bus of a DIGIT 3000
application. The Picture Bus Priority lines carry the digi-
tal priority selection signals. The priority interface allows
digital switching of up to 8 sources to the backend pro-
cessor. Switching for different sources is prioritized and
can be on a per pixel basis. In all other applications, they
must not be connected.
Pin 18 – PVSS Output Pin Ground
This is the common ground connection of all output
stages and must be connected to ground.
Note: All ground pins of the chip (i.e. 18, 52, 58, 60, 62,
64, 66, and 68) must be connected together low resis-
tive. The layout of the PCB must take into consideration
the need for a low-noise ground.
Pins 36 to 43 – C0 to C7 Chroma Input (Fig. 3–8)
These are the inputs for the digital chroma signal which
can be received in binary offset or 2’s complement
coded format. In a DIGIT 2000 (4:1:1) system, C3 to C0
take the halfbyte (nibble) multiplex format. C7 to C4
have to be connected to ground. Within the DIGIT 3000
(4:2:2) system, U and V are multiplexed bytewise. Con-
nect to ground if not used.
Pin 19 – PVDD Output Pin Supply +5 V / +3.3 V
This pin supplies all output stages and must be con-
nected to a positive supply voltage.
Note:ThelayoutofthePCBmusttakeintoconsideration
the need for a low-noise supply. A bypass capacitor has
to be connected between ground and PVDD
(see section 4. Application Circuit.
Pins 44 to 51 – L0 to L7 Luma Input (Fig. 3–8)
These are the inputs for the digital luma signal which
must be in pure binary coded format. Connect to ground
if not used.
Pin 52 – DVSS Digital Ground
This is the common ground connection of all digital
stages and must be connected to ground.
Pins 20 to 27 – RC7 to RC0 Red/Chroma Output
(Fig. 3–3 )
Note: All ground pins of the chip (i.e. 18, 52, 58, 60, 62,
64, 66, and 68) must be connected together low resis-
tive. The layout of the PCB must take into consideration
the need for a low-noise ground.
These are the outputs for the digital chroma signal in the
DIGIT 3000 system, where U and V are multiplexed
bytewise. In a DIGIT 2000 system, RC3 to RC0 and RC7
to RC4 carry the halfbyte (nibble) multiplex format. In a
stand alone application, where the CIP 3250A serves as
an AD-converter, these are the outputs for the digital
Red signal (pure binary) or the digital chroma V signal
(2’s complement). Leave vacant if not used.
Pin 53 – DVDD Digital Supply +5 V
This pin supplies all digital stages and must be con-
nected to a positive supply voltage.
Note:ThelayoutofthePCBmusttakeintoconsideration
the need for a low-noise supply. A bypass capacitor has
to be connected between ground and DVDD
(see section 4. Application Circuit.
Pin 28 – AVO Active Video Output (Fig. 3–4)
This output provides the Active Video signal, which car-
ries information about the chroma multiplex in a DIGIT
3000 application and indicates valid video data at the
Luma/Chroma outputs. This signal is programmable via
Pin 54 – CLK Main Clock Input (Fig. 3–9)
This is the input for the clock signal. The frequency can
vary in the range from 13.5 MHz to 20.25 MHz.
2
I C registers. Leave vacant if not used.
30
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