CIP 3250A
ADVANCE INFORMATION
Sub-
Address
(decimal)
Label
Bit No.
(LSB = 0)
Typical
Operation
Value
Function
2
I C registers for OUTPUT CONTROL
06
09
14
14
HALFOUT
AVODIS
PUDIS
4
0
0
0
0
Output drive duration
0 = output active a full clock cycle (only one IC on Picture Bus)
1 = output active half a clock cycle (more than one IC on Picture Bus)
1
disable AVO pin
0 = AVO pin is active
1 = AVO pin is tristate
3
disable pull-up transistors at GL, RC, and B output pins
0 = pull-up on (output is in push-pull mode)
1 = pull-up off (output is in open drain mode)
LOAD
2–0
adjust load of AVO, GL, RC, B and PRIO
(select lowest possible load to keep electromagnetic radiation
and noise at A/D-Converter low)
LOAD|
GL, RC, B, and AVO outputs
|
@PVDD = 5 Volt
|
@PVDD = 3.3 Volt
000 | C
001 | C
010 | C
011 | C
100 | C
101 | C
110 | C
v100 pF I
v3.4mA| C
v2.3mA| C
v1.5mA| C
v1.2mA| C
v0.9mA| C
v0.7mA| C
v0.6mA| C
v50 pF
v28 pF
v20 pF
v16 pF
v12 pF
v10 pF
v8 pF
I
I
I
I
I
I
I
v3.0mA
v1.5mA
v1.0mA
v0.8mA
v0.6mA
v0.5mA
v0.4mA
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
v55 pF
v37 pF
v28 pF
v23 pF
v18 pF
v14 pF
I
I
I
I
I
I
111 | pins tristate
| pins tristate
LOAD|
PRIO bus
000 | I
001 | I
010 | I
011 | I
100 | I
101 | I
110 | I
111 | I
v12mA
v12mA
v9mA
v9mA
v6mA
v6mA
v3mA
v3mA
SINK
SINK
SINK
SINK
SINK
SINK
SINK
SINK
NOTE:
Total C
at pins GL, RC, B, AVO, and PRIO must not exceed 2 nF.
LOAD
C
C
= max. load capacitance for AVO
= max. load capacitance for GL, RC, and B at push-pull mode
Load
Load
12C:<14> PUDIS = 0
= max. sink current for GL, RC, and B at open drain mode
I
Load
12C:<14> PUDIS = 1
Micronas
25
MICRONAS [ MICRONAS ]
