CAP 3001 A
2.1.22. Clock Generation
Following the clock oscillator is a frequency multiplier
with a factor of 3. The output of the frequency multiplier
delivers the f
DSP Core is clocked.
internal clock frequency, by which the
The CAP 3001 A processor has an integrated clock os-
cillator which is crystal-controlled and oscillates with the
ICLK
frequency f
+16.416 MHz. All components of the
ECLK
oscillator are integrated except for the quartz crystal.
This is connected to the QX1 and QX2 oscillator pins.
The crystal input QX2/ECLK can be used to supply the
CAP 3001 A externally with the required clock. In this
case no crystal is needed.
There is the possibility of pulling the f
oscillator fre-
ECLK
quencyinarangeof350ppm, dependingontheapplica-
tion and the used crystal. This makes it possible to syn-
chronize the CAP 3001 A to the incoming pilot tone
signal in the case of MPX reception.
Table 2–1: Oscillator characteristics
DCO Content
Frequency
011111111B
000000000B
100000000B
f
f
f
ECLKmin
ECLK
ECLKmax
DCO Clock
Control
9
Register
1 nF
39
38
ECLK
39
Clock
Oscillator
f
ECLK
38
100 nF
Frequency
Multiplier
GNDD
external option
f
ICLK
Φ1
Clock
Pulse
Φ2
Φ3
Φ4
Shaper
and
62
CLKOUT
Frequency
Divider
Fig. 2–17: Clock generator connections
MICRONAS INTERMETALL
17
MICRONAS [ MICRONAS ]
