CAP 3001 A
Tbck
16, 24, 32 x Tbck
SCLK_IN/OUT
WS_IN/OUT
polarity
programmable
1 Tbck: programmable
SDATA
ERR
MSB
LSB
LSB
MSB
MSB/LSB first programmable
0, 8, 16 x Tbck: programmable delay
Fig. 2–13: Timing of the signals
Tbck+1/Fbck
Fbck+32@Fsaudio or
Fbck+48@Fsaudio or
Fbck+64@Fsaudio
The modes are:
In all modes:
MSB or LSB-first can be selected;
one bit delay between active slope of WSI/O and first
wordframe bit is programmable;
– 16-bit wordframe
in this case the programmable delay is set to zero;
the polarity of WSI/O can be programmed ;
in the 24 and 32-bit wordframes the open data bit loca-
tions are MSB or LSB extended (depends on left or right
adjustment).
– 24-bit wordframe
in this case the programmable delay is set either to 0
or to 8 Tbck;
this allows left or right adjusted handling of the 16 data
bits
Input format and output format can be programmed sep-
arately. The restrictions are:
– 32-bit wordframe
in this case the programmable delay is set either to 0
or to 16 Tbck;
this allows left or right adjusted handling of the 16 data
bits.
A 24-bit wordframe can only be sent if a 24-bit word-
frame is also received. In the analog input mode, the
24-bit wordframe output is not allowed.
14
MICRONAS INTERMETALL
MICRONAS [ MICRONAS ]
