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CAP3001A 参数 Datasheet PDF下载

CAP3001A图片预览
型号: CAP3001A
PDF下载: 下载PDF文件 查看货源
内容描述: 汽车音响处理器硬件 [Car Audio Processor Hardware]
分类和应用: 汽车音响
文件页数/大小: 37 页 / 461 K
品牌: MICRONAS [ MICRONAS ]
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CAP 3001 A  
2.1.14. FM Noise Canceller (ASU)  
2.1.17. Lowpass-Filters ALPF  
The analog lowpass-filters behind the DACs eliminate  
the high-frequent noise in order to avoid any distortions  
in the AM frequency range.  
The FM Noise Canceller removes peak noise from the  
audio signal. No external circuitry is required. All filters,  
delays and the control section are implemented digitally.  
The function is split into two sections:  
2.1.18. Volume Control AVOL  
– The noise detection searches for energy in the non-  
audio range by means of a highpass filter. The output  
of this filter is compared with a DSP-controlled thresh-  
old. If this threshold is exceeded the interpolation unit  
is triggered. The 19 kHz pilot tone is removed before  
the audio signal enters the detection highpass. Pro-  
grammable delay adjustment makes sure of the cor-  
rect timing between peak detection and peak inter-  
polation.  
The analog volume control together with the digital vol-  
ume control implemented in the digital signal proces-  
sor’s software provide a large volume control range. The  
analog volume control itself covers a range of 45 dB in  
1.5 dB steps and includes an additional mute position.  
A sensible splitting of the total gain v_tot between the  
digital gain v_dig and the analog gain v_anlg is:  
– The interpolation circuit substitutes a peak-corrupted  
sample by the mean value of the non-corrupted adja-  
cent samples. Once a trigger comes from the detec-  
tion circuit, a programmable number (0 to 15) of  
successive samples is interpolated. All functions work  
on a 228 kHz sampling rate. At this rate the peaks are  
still small enough (not widened by the final decimation  
filters) to be removed effectively.  
v_tot  
v_anlg  
0 dB  
v_dig  
v_totw0 dB  
v_tot  
*45 dBtv_tott0 dB  
v_tott*45 dB  
v_tot  
0 dB  
*45 dB  
v_tot)45 dB  
All control bits for the hardware section are first ad-  
dressed to the DSP core program. In case of hardware  
read-registers the bits are transmitted to the DSP core,  
stored in the DSP RAM and so they are available for the  
controller via the DSP’s IM-bus interface.  
2.1.15. Analog Output Systems  
2.1.16. D/A-Converters DAC  
The D/A-converters used are of the oversampling type.  
The samples to be converted at their sampling rate f_s  
are first interpolated to 8 x the sampling rate and then  
oversampled to a higher rate f_NS where noise shaping  
is performed. The output of the noise shaper is then con-  
vertedusingahighlylinearD/A-converter. Itsnoisepow-  
er density increases with increasing frequency, the re-  
sidual noise in the baseband is very low.  
Within this application the DAC has to be adapted to the  
different modes. The digital sources (e.g. CD-player)  
must supply the proper clock rate in order to drive the  
DAC with a stable clock rate locked to the sampling rate.  
TheclockisderivedfromtheclocklineSCLKofthePDAI  
bus.  
12  
MICRONAS INTERMETALL  
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