128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
Features
List of Figures
Figure 1: 64-Ball Easy BGA (8mm x 10mm x 1.2mm) ....................................................................................... 13
Figure 2: 64-Ball Easy BGA (Top View, Balls Down) ......................................................................................... 14
Figure 3: Main Array Word Lines .................................................................................................................... 19
Figure 4: Wrap/No-Wrap Example ................................................................................................................. 19
Figure 5: End-of-Wordline Delay .................................................................................................................... 19
Figure 6: Two-Cycle Command Sequence ....................................................................................................... 21
Figure 7: Single-Cycle Command Sequence .................................................................................................... 21
Figure 8: READ Cycle Between WRITE Cycles ................................................................................................. 21
Figure 9: Illegal Command Sequence ............................................................................................................. 22
Figure 10: Configurable Programming Regions: Control Mode and Object Mode .............................................. 34
Figure 11: Configurable Programming Regions: Control Mode and Object Mode Segments .............................. 36
Figure 12: BLOCK LOCK Operations ............................................................................................................... 47
Figure 13: OTP Area Map ............................................................................................................................... 49
Figure 14: VPP Supply Connection Example .................................................................................................... 51
Figure 15: RESET Operation Waveforms ......................................................................................................... 54
Figure 16: AC Input/Output Reference Waveform ........................................................................................... 61
Figure 17: Transient Equivalent Testing Load Circuit ....................................................................................... 61
Figure 18: Clock Input AC Waveform .............................................................................................................. 62
Figure 19: Asynchronous Page-Mode Read (Non-MUX) .................................................................................. 65
Figure 20: Synchronous 8- or 16-Word Burst Read (Non-MUX) ........................................................................ 66
Figure 21: Synchronous Continuous Misaligned Burst Read (Non-MUX) ......................................................... 67
Figure 22: Synchronous Burst with Burst Interrupt Read (Non-MUX) .............................................................. 68
Figure 23: Asynchronous Single-Word Read .................................................................................................... 69
Figure 24: Synchronous 8- or 16-Word Burst Read (A/D MUX) ......................................................................... 70
Figure 25: Synchronous Continuous Misaligned Burst Read (A/D MUX) .......................................................... 71
Figure 26: Synchronous Burst with Burst-Interrupt (AD-Mux) ......................................................................... 71
Figure 27: Write Timing ................................................................................................................................. 74
Figure 28: Write to Write (Non-Mux) .............................................................................................................. 75
Figure 29: Async Read to Write (Non-Mux) ..................................................................................................... 75
Figure 30: Write to Async Read (Non-Mux) ..................................................................................................... 76
Figure 31: Sync Read to Write (Non-Mux) ....................................................................................................... 76
Figure 32: Write to Sync Read (Non-Mux) ....................................................................................................... 77
Figure 33: Write to Write (AD-Mux) ................................................................................................................ 77
Figure 34: Async Read to Write (AD-Mux) ....................................................................................................... 78
Figure 35: Write to Async Read (AD-Mux) ....................................................................................................... 78
Figure 36: Sync Read to Write (AD-Mux) ......................................................................................................... 79
Figure 37: Write to Sync Read (AD-Mux) ......................................................................................................... 79
Figure 38: Word Program Procedure ............................................................................................................... 92
Figure 39: Word Program Full Status Check Procedure .................................................................................... 93
Figure 40: Program Suspend/Resume Procedure ............................................................................................ 94
Figure 41: Buffer Programming Procedure ...................................................................................................... 96
Figure 42: Buffered Enhanced Factory Programming (BEFP) Procedure ........................................................... 98
Figure 43: Block Erase Procedure .................................................................................................................. 100
Figure 44: Block Erase Full Status Check Procedure ........................................................................................ 101
Figure 45: Erase Suspend/Resume Procedure ................................................................................................ 102
Figure 46: Block Lock Operations Procedure .................................................................................................. 104
Figure 47: Protection Register Programming Procedure ................................................................................. 105
Figure 48: Protection Register Programming Full Status Check Procedure ....................................................... 106
Figure 49: Blank Check Procedure ................................................................................................................. 107
Figure 50: Blank Check Full Status Check Procedure ...................................................................................... 108
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
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