P30-65nm
Table 15: End of Wordline Data and WAIT state Comparison
P30-130nm
P30-65nm
Latency Count
Data States
WAIT States
Data States
WAIT States
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Not Supported
Not Supported
0 to 1
Not Supported
Not Supported
Not Supported
Not Supported
Not Supported
Not Supported
Not Supported
Not Supported
0 to 4
4
4
4
4
4
4
0 to 2
0 to 3
0 to 4
0 to 5
16
16
16
16
16
16
16
16
16
16
16
0 to 5
0 to 6
0 to 7
0 to 8
0 to 9
0 to 10
0 to 11
0 to 12
0 to 6
Not Supported
Not Supported
0 to 13
0 to 14
11.2.4
WAIT Polarity (RCR.10)
The WAIT Polarity bit (WP), RCR.10 determines the asserted level (VOH or VOL) of WAIT.
When WP is set, WAIT is asserted high. When WP is cleared, WAIT is asserted low
(default). WAIT changes state on valid clock edges during active bus cycles (CE#
asserted, OE# asserted, RST# deasserted).
Table 16: WAIT Functionality Table
Condition
WAIT
Notes
CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’
CE# =’0’, OE# = ‘0’
High-Z
Active
1
1
Synchronous Array Reads
Synchronous Non-Array Reads
All Asynchronous Reads
All Writes
Active
1
Active
1
Deasserted
High-Z
1
1,2
Notes:
1.
2.
Active: WAIT is asserted until data becomes valid, then deasserts.
When OE# = V during writes, WAIT = High-Z.
IH
11.2.5
11.2.6
WAIT Delay (RCR.8)
The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during
synchronous burst reads. WAIT can be asserted either during or one data cycle before
valid data is output on DQ[15:0]. When WD is set, WAIT is deasserted one data cycle
before valid data (default). When WD is cleared, WAIT is deasserted during valid data.
Burst Sequence (RCR.7)
The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst
sequence is supported. Table 17 shows the synchronous burst sequence for all burst
lengths, as well as the effect of the Burst Wrap (BW) setting.
Datasheet
39
Sept 2012
OrderNumber:208042-06
MICRON [ MICRON TECHNOLOGY ]
