P30-65nm
Table 13: Read Configuration Register Description (Sheet 2 of 2)
Burst Wrap (BW)
0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]
1 =No Wrap; Burst accesses do not wrap within burst length (default)
3
001 =4-word burst
010 =8-word burst
011 =16-word burst
111 =Continuous-word burst (default)
2:0
Burst Length (BL[2:0])
(Other bit settings are reserved)
11.2.1
11.2.2
Read Mode (RCR.15)
The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode
operation for the device. When the RM bit is set, asynchronous page mode is selected
(default). When RM is cleared, synchronous burst mode is selected.
Latency Count (RCR[14:11])
The Latency Count (LC) bits tell the device how many clock cycles must elapse from the
rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the
first valid data word is driven onto DQ[15:0]. The input clock frequency is used to
determine this value and Figure 10 shows the data output latency for the different
settings of LC. The maximum Latency Count for P30-65nm would be Code 5 based on
the Max clock frequency specification of 52MHz, and there will be zero WAIT States
when bursting within the word line. Please also refer to Section 11.2.3, “End of Word
Line (EOWL) Considerations” on page 38 for more information on EOWL.
Refer to Table 14, “LC and Frequency Support” on page 37 for Latency Code Settings.
Datasheet
36
Sept 2012
Order Number: 208042-06
MICRON [ MICRON TECHNOLOGY ]
