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PC28F00BP30EFA 参数 Datasheet PDF下载

PC28F00BP30EFA图片预览
型号: PC28F00BP30EFA
PDF下载: 下载PDF文件 查看货源
内容描述: Numonyx® Axcellâ ?? ¢ P30-65nm闪存 [Numonyx® Axcell™ P30-65nm Flash Memory]
分类和应用: 闪存内存集成电路
文件页数/大小: 86 页 / 11765 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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P30-65nm  
11.2  
Read Configuration Register (RCR) (Easy BGA)  
The RCR is a 16-bit read/write register used to select bus-read mode (synchronous or  
asynchronous), and to configure synchronous burst read characteristics of the device.  
To modify RCR settings, use the Configure Read Configuration Register command (see  
Section 6.2, “Device Command Bus Cycles” on page 20).  
RCR contents can be examined using the Read Device Identifier command, and then  
reading from offset 0x05 (see Section 7.2, “Read Device Identifier” on page 22).  
Upon power-up or exit from reset, the RCR defaults to asynchronous mode.  
The RCR is shown in Table 13. The following sections describe each RCR bit function.  
Table 13: Read Configuration Register Description (Sheet 1 of 2)  
Read Configuration Register (RCR)  
WAIT  
Delay  
Burst  
Wrap  
Read  
Mode  
WAIT  
Burst  
Seq  
CLK  
Latency Count  
LC[3:0]  
RES  
RES  
RES  
Burst Length  
Polarity  
Edge  
RM  
15  
Bit  
WP  
10  
R
9
WD  
8
BS  
7
CE  
6
R
5
R
4
BW  
3
BL[2:0]  
1
14  
13  
12  
11  
2
0
Name  
Description  
0 = Synchronous burst-mode read  
1 = Asynchronous page-mode read (default)  
15  
Read Mode (RM)  
0011 =Code 3  
0100 =Code 4  
0101 =Code 5  
0110 =Code 6  
0111 =Code 7  
1000 =Code 8  
1001 =Code 9  
14:11  
Latency Count (LC[3:0])  
1010 =Code 10  
1011 =Code 11  
1100 =Code 12  
1101 =Code 13  
1110 =Code 14  
1111 =Code 15 (default)  
(Other bit settings are reserved)  
0 =WAIT signal is active low (default)  
1 =WAIT signal is active high  
WAIT Polarity (WP)  
10  
9
Reserved (R)  
Default “0, Non-changeable  
0 =WAIT deasserted with valid data  
8
WAIT Delay (WD)  
Burst Sequence (BS)  
1 =WAIT deasserted one data cycle before valid data (default)  
7
Default “0, Non-changeable  
Clock Edge (CE)  
Reserved (R)  
0 = Falling edge  
1 = Rising edge (default)  
6
5:4  
Reserved bits should be cleared (0)  
Datasheet  
35  
Sept 2012  
OrderNumber:208042-06  
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