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N25Q512A83GSF40G 参数 Datasheet PDF下载

N25Q512A83GSF40G图片预览
型号: N25Q512A83GSF40G
PDF下载: 下载PDF文件 查看货源
内容描述: 美光的串行NOR闪存3V ,多个I / O, 4KB扇区擦除N25Q512A [Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A]
分类和应用: 闪存
文件页数/大小: 91 页 / 1214 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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512Mb, Multiple I/O Serial Flash Memory  
ONE-TIME PROGRAMMABLE Operations  
ONE-TIME PROGRAMMABLE Operations  
READ OTP ARRAY Command  
To initiate a READ OTP ARRAY command, S# is driven LOW. The command code is in-  
put on DQ0, followed by address bytes and dummy clock cycles. Each address bit is  
latched in during the rising edge of C. Data is shifted out on DQ1, beginning from the  
specified address and at a maximum frequency of fC (MAX) on the falling edge of the  
clock. The address increments automatically to the next address after each byte of data  
is shifted out. There is no rollover mechanism; therefore, if read continuously, after lo-  
cation 0x40, the device continues to output data at location 0x40. The operation is ter-  
minated by driving S# HIGH at any time during data output.  
Figure 35: READ OTP Command  
Extended  
0
7
8
Cx  
C
LSB  
A[MIN]  
DQ0  
DQ1  
Command  
MSB  
A[MAX]  
LSB  
DOUT DOUT  
DOUT  
MSB  
DOUT  
DOUT  
DOUT  
DOUT  
DOUT  
DOUT  
High-Z  
Dummy cycles  
Dual  
0
3
4
Cx  
C
LSB  
A[MIN]  
LSB  
DOUT DOUT  
DOUT  
MSB  
DOUT  
DOUT  
DQ[1:0]  
Command  
MSB  
A[MAX]  
Dummy cycles  
Quad  
0
1
2
Cx  
C
LSB  
A[MIN]  
LSB  
DOUT  
DOUT  
MSB  
DOUT  
DQ[3:0]  
Command  
MSB  
A[MAX]  
Don’t Care  
Dummy cycles  
1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1).  
For dual SPI protocol, Cx = 3 + (A[MAX] + 1)/2.  
For quad SPI protocol, Cx = 1 + (A[MAX] + 1)/4.  
Note:  
PROGRAM OTP ARRAY Command  
To initiate the PROGRAM OTP ARRAY command, the WRITE ENABLE command must  
be issued to set the write enable latch bit to 1; otherwise, the PROGRAM OTP ARRAY  
command is ignored and flag status register bits are not set. S# is driven LOW and held  
LOW until the eighth bit of the last data byte has been latched in, after which it must be  
driven HIGH. The command code is input on DQ0, followed by address bytes and at  
least one data byte. Each address bit is latched in during the rising edge of the clock.  
When S# is driven HIGH, the operation, which is self-timed, is initiated; its duration is  
tPOTP. There is no rollover mechanism; therefore, after a maximum of 65 bytes are  
latched in the subsequent bytes are discarded.  
PDF: 09005aef84752721  
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
68  
© 2011 Micron Technology, Inc. All rights reserved.