512Mb, Multiple I/O Serial Flash Memory
ONE-TIME PROGRAMMABLE Operations
PROGRAM OTP ARRAY programs, at most, 64 bytes to the OTP memory area and one
OTP control byte. When the operation is in progress, the write in progress bit is set to 1.
The write enable latch bit is cleared to 0, whether the operation is successful or not, and
the status register and flag status register can be polled for the operation status. When
the operation completes, the write in progress bit is cleared to 0.
If the operation times out, the write enable latch bit is reset and the program fail bit is
set to 1. If S# is not driven HIGH, the command is not executed, flag status register error
bits are not set, and the write enable latch remains set to 1. The operation is considered
complete once bit 7 of the flag status register outputs 1 with at least one byte output.
The OTP control byte (byte 64) is used to permanently lock the OTP memory array.
Table 30: OTP Control Byte (Byte 64)
Bit Name
OTP control byte
Settings
Description
0
0 = Locked
1 = Unlocked (Default)
Used to permanently lock the 64-byte OTP array. When bit 0 = 1,
the 64-byte OTP array can be programmed. When bit 0 = 0, the
64-byte OTP array is read only.
Once bit 0 has been programmed to 0, it can no longer be
changed to 1. Program OTP array is ignored, the write enable
latch bit remains set, and flag status register bits 1 and 4 are set.
Figure 36: PROGRAM OTP Command
Extended
0
7
8
Cx
C
LSB
A[MIN]
LSB
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DQ[0]
Command
MSB
A[MAX]
MSB
Dual
0
3
4
Cx
C
LSB
A[MIN]
LSB
DIN
DIN
DIN
DIN
DIN
DQ[1:0]
Command
MSB
A[MAX]
MSB
Quad
0
1
2
Cx
C
LSB
A[MIN]
LSB
DIN
DIN
DIN
DQ[3:0]
Command
MSB
A[MAX]
MSB
1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1).
For dual SPI protocol, Cx = 3 + (A[MAX] + 1)/2.
For quad SPI protocol, Cx = 1 + (A[MAX] + 1)/4.
Note:
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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