512Mb, Multiple I/O Serial Flash Memory
RESET Operations
RESET Operations
RESET ENABLE and RESET MEMORY Command
To reset the device, the RESET ENABLE command must be followed by the RESET
MEMORY command. To execute each command, S# is driven LOW. The command code
is input on DQ0. A minimum de-selection time of tSHSL2 must come between the RE-
SET ENABLE and RESET MEMORY commands or a reset is not guaranteed. When these
two commands are executed and S# is driven HIGH, the device enters a power-on reset
condition. A time of tSHSL3 is required before the device can be re-selected by driving
S# LOW. It is recommended that the device exit XIP mode before executing these two
commands to initiate a reset.
All volatile lock bits, the volatile configuration register, the enhanced volatile configura-
tion register, and the extended address register are reset to the power-on reset default
condition. The power-on reset condition depends on settings in the nonvolatile config-
uration register.
If a reset is initiated while a WRITE, PROGRAM, or ERASE operation is in progress or
suspended, the operation is aborted and data may be corrupted. Reset is effective once
bit 7 of the flag status register outputs 1 with at least one byte output. A RESET ENABLE
command is not accepted in the cases of WRITE STATUS REGISTER and WRITE NON-
VOLATILE CONFIGURATION REGISTER operations.
Figure 34: RESET ENABLE and RESET MEMORY Command
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
C
S#
Reset enable
Reset memory
DQ0
1. The number of lines and rate for transmission varies with extended, dual, or quad SPI.
Note:
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN
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