欢迎访问ic37.com |
会员登录 免费注册
发布采购

N25Q512A13GF840E 参数 Datasheet PDF下载

N25Q512A13GF840E图片预览
型号: N25Q512A13GF840E
PDF下载: 下载PDF文件 查看货源
内容描述: 美光的串行NOR闪存3V ,多个I / O, 4KB扇区擦除N25Q512A [Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A]
分类和应用: 闪存
文件页数/大小: 91 页 / 1214 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号N25Q512A13GF840E的Datasheet PDF文件第56页浏览型号N25Q512A13GF840E的Datasheet PDF文件第57页浏览型号N25Q512A13GF840E的Datasheet PDF文件第58页浏览型号N25Q512A13GF840E的Datasheet PDF文件第59页浏览型号N25Q512A13GF840E的Datasheet PDF文件第61页浏览型号N25Q512A13GF840E的Datasheet PDF文件第62页浏览型号N25Q512A13GF840E的Datasheet PDF文件第63页浏览型号N25Q512A13GF840E的Datasheet PDF文件第64页  
512Mb, Multiple I/O Serial Flash Memory  
ERASE Operations  
ERASE Operations  
When the operation is in progress, the program or erase controller bit of the flag status  
register is set to 0. The flag status register must be polled for the operation status. When  
the operation completes, that bit is cleared to 1.  
Note that the flag status register must be polled even if operation times out.  
SUBSECTOR ERASE Command  
To execute the SUBSECTOR ERASE command (and set the selected subsector bits to  
FFh), the WRITE ENABLE command must be issued to set the write enable latch bit to  
1. S# is driven LOW and held LOW until the eighth bit of the last data byte has been  
latched in, after which it must be driven HIGH. The command code is input on DQ0,  
followed by address bytes; any address within the subsector is valid. Each address bit is  
latched in during the rising edge of the clock. When S# is driven HIGH, the operation,  
which is self-timed, is initiated; its duration is tSSE. The operation can be suspended  
and resumed by the PROGRAM/ERASE SUSPEND and PROGRAM/ERASE RESUME  
commands, respectively.  
If the write enable latch bit is not set, the device ignores the SUBSECTOR ERASE com-  
mand and no error bits are set to indicate operation failure.  
When the operation is in progress, the program or erase controller bit is set to 0. The  
write enable latch bit is cleared to 0, whether the operation is successful or not. The sta-  
tus register and flag status register can be polled for the operation status. The operation  
is considered complete once bit 7 of the flag status register outputs 1 with at least one  
byte output. When the operation completes, the program or erase controller bit is  
cleared to 1.  
If the operation times out, the write enable latch bit is reset and the erase error bit is set  
to 1. If S# is not driven HIGH, the command is not executed, flag status register error  
bits are not set, and the write enable latch remains set to 1. When a command is applied  
to a protected subsector, the command is not executed. Instead, the write enable latch  
bit remains set to 1, and flag status register bits 1 and 5 are set.  
SECTOR ERASE Command  
To execute the SECTOR ERASE command (and set selected sector bits to FFh), the  
WRITE ENABLE command must be issued to set the write enable latch bit to 1. S# is  
driven LOW and held LOW until the eighth bit of the last data byte has been latched in,  
after which it must be driven HIGH. The command code is input on DQ0, followed by  
address bytes; any address within the sector is valid. Each address bit is latched in dur-  
ing the rising edge of the clock. When S# is driven HIGH, the operation, which is self-  
timed, is initiated; its duration is tSE. The operation can be suspended and resumed by  
the PROGRAM/ERASE SUSPEND and PROGRAM/ERASE RESUME commands, respec-  
tively.  
If the write enable latch bit is not set, the device ignores the SECTOR ERASE command  
and no error bits are set to indicate operation failure.  
When the operation is in progress, the program or erase controller bit is set to 0. The  
write enable latch bit is cleared to 0, whether the operation is successful or not. The sta-  
tus register and flag status register can be polled for the operation status. The operation  
is considered complete once bit 7 of the flag status register outputs 1 with at least one  
PDF: 09005aef84752721  
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
60  
© 2011 Micron Technology, Inc. All rights reserved.  
 复制成功!