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N25Q512A13GF840E 参数 Datasheet PDF下载

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型号: N25Q512A13GF840E
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内容描述: 美光的串行NOR闪存3V ,多个I / O, 4KB扇区擦除N25Q512A [Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A]
分类和应用: 闪存
文件页数/大小: 91 页 / 1214 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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512Mb, Multiple I/O Serial Flash Memory  
ERASE Operations  
byte output. When the operation completes, the program or erase controller bit is  
cleared to 1.  
The command is not executed if any sector is locked. Instead, the write enable latch bit  
remains set to 1, and flag status register bits 1 and 5 are set.  
Figure 32: DIE ERASE Command  
Extended  
0
7
8
4
C
x
C
LSB  
A[MIN]  
DQ0  
Command  
MSB  
A[MAX]  
A[MAX]  
Dual  
0
3
C
x
C
LSB  
A[MIN]  
DQ0[1:0]  
Command  
MSB  
Quad  
0
1
2
C
x
C
LSB  
A[MIN]  
DQ0[3:0]  
Command  
MSB  
A[MAX]  
1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1).  
For dual SPI protocol, Cx = 3 + (A[MAX] + 1)/2.  
For quad SPI protocol, Cx = 1 + (A[MAX] + 1)/4.  
Note:  
BULK ERASE Command  
The BULK ERASE command is valid for part numbers N25Q512A83GSF40x and  
N25Q512A83G1240x. To initiate the BULK ERASE command, the WRITE ENABLE com-  
mand must be issued to set the write enable latch bit to 1. S# is driven LOW and held  
LOW until the eighth bit of the last data byte has been latched in, after which it must be  
driven HIGH. The command code is input on DQ0. When S# is driven HIGH, the opera-  
tion, which is self-timed, is initiated; its duration is tBE.  
If the write enable latch bit is not set, the device ignores the SECTOR ERASE command  
and no error bits are set to indicate operation failure.  
When the operation is in progress, the write in progress bit is set to 1 and the write ena-  
ble latch bit is cleared to 0, whether the operation is successful or not. The status regis-  
ter and flag status register can be polled for the operation status. When the operation  
completes, the write in progress bit is cleared to 0.  
If the operation times out, the write enable latch bit is reset and erase error bit is set to  
1. If S# is not driven HIGH, the command is not executed, the flag status register error  
bits are not set, and the write enable latch remains set to 1.  
PDF: 09005aef84752721  
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
62  
© 2011 Micron Technology, Inc. All rights reserved.  
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