512Mb, Multiple I/O Serial Flash Memory
Memory Organization
Memory Organization
Memory Configuration and Block Diagram
The memory is a stacked device comprised of two 256Mb chips. Each chip is internally
partitioned into two 128Mb segments. Each page of memory can be individually pro-
grammed. Bits are programmed from one through zero. The device is subsector, sector,
or single 256Mb chip erasable, but not page-erasable. Bits are erased from zero through
one. The memory is configured as 67,108,864 bytes (8 bits each); 1024 sectors (64KB
each); 16,384 subsectors (4KB each); and 262,144 pages (256 bytes each); and 64 OTP
bytes are located outside the main memory array.
Figure 4: Block Diagram
HOLD#
W#/VPP
S#
High voltage
Control logic
generator
64 OTP bytes
C
DQ0
DQ1
DQ2
DQ3
I/O shift register
Address register
and counter
256 byte
data buffer
Status
register
03FFFFFFh
0000000h
00000FFh
256 bytes (page size)
X decoder
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN
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