512Mb, Multiple I/O Serial Flash Memory
Device Description
XIP Mode
XIP mode requires only an address (no instruction) to output data, improving random
access time and eliminating the need to shadow code onto RAM for fast execution.
Nonvolatile configuration register bits can set XIP mode as the default mode for appli-
cations that must enter XIP mode immediately after powering up.
All protocols support XIP operation. For flexibility, multiple XIP entry and exit methods
are available. For applications that must enter XIP mode immediately after power-up,
nonvolatile configuration register bit settings can enable XIP as the default mode.
Device Configurability
The N25Q family offers additional features that are configured through the nonvolatile
configuration register for default and/or nonvolatile settings. Volatile settings can be
configured through the volatile and volatile-enhanced configuration registers. These
configurable features include the following:
• Number of dummy cycles for the fast READ commands
• Output buffer impedance
• SPI protocol types (extended SPI, dual SPI, or quad SPI)
• Required XIP mode
• Enabling/disabling HOLD (RESET function)
• Enabling/disabling wrap mode
Figure 1: Logic Diagram
VCC
DQ0
DQ1
C
NOR die 2
NOR die 1
S#
VPP/W#/DQ2
HOLD#/DQ3
RESET
VSS
1. Reset functionality is available in devices with a dedicated part number. See Part Num-
ber Ordering Information for more details. The RESET pin is available only for part num-
bers N25Q512A83G1240X and N25Q512A83GSF40X. On these two parts, the additional
RESET pin must be connected to an external pull-up.
Note:
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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