N25Q128 - 1.8 V
Instructions
Note:
Reset functionality is available instead of Hold in devices with a dedicated part number. See
Section 16: Ordering information.
Figure 15. Quad Input/Output Fast Read instruction sequence
S
C
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12
14 15 16
21 22 23 24 25 26
27
13
5
IO switches from Input to Output
Instruction
Address
0
1
2
3
4
0
4
0
DQ0
DQ1
DQ2
4
4
6
7
Don’t Care
Don’t Care
5
1
2
5
6
1
2
5
6
6
DQ3
7
3
7
3
7
‘1’
A7-0
Dummy (ex.: 10)
Byte 2
Byte 1
A15-8
A23-16
Quad_Output_Fast_Read
9.1.7
Quad I/O Fast Read
The Quad I/O Fast Read (QIOFR) instruction is very similar to the Quad Output Fast Read
(QOFR), except that the address bits are shifted in on four pins (pin DQ0, pin DQ1, pin
W/VPP/DQ2 and pin HOLD/DQ3 (1)) instead of only one.
Note:
Reset functionality is available instead of Hold in devices with a dedicated part number. See
Section 16: Ordering information.
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