N25Q128 - 1.8 V
Instructions
Figure 17. Read OTP instruction and data-out sequence
S
C
0
1
2
3
4
5
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7
8
9
10
28 29 30 31
Instruction
24-bit address
23 22 21
3
2
1
0
DQ0
DQ1
High Impedance
S
C
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
Dummy cycles
7
6
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4
3
2
0
1
DQ0
DQ1
DATA OUT n
DATA OUT 1
7
6
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2
1
0
7
7
6
5
4
3
2
0
1
MSB
MSB
MSB
Read _OTP
9.1.9
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every Program, Erase or Write
instructions:
Page Program (PP), Dual Input Fast Program (DIFP), Dual Input Extended Fast Program
(DIEFP), Quad Input Fast Program (QIFP), Quad Input Extended Fast Program (QIEFP),
Program OTP (POTP), Write to Lock Register (WRLR), Subsector Erase (SSE), Sector
Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Configuration Register
(WRCR), Write Enhanced Configuration Register (WRECR) and Write NV Configuration
Register (WRNVCR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
When the Fast POR feature is selected (Non Volatile Configuration Register bit 5) after the
first Write Enable instruction, the device enters in a latency time (~500 us), necessary to
internally complete the POR sequence with the modify algorithms. (See Section 11.1: Fast
POR.) During the POR latency time all the instructions are ignored with the exception of the
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