Volatile and Non Volatile Registers
N25Q128 - 1.8 V
Table 6.
Bit
Volatile Configuration Register
Parameter
Value
0000
Description
As '1111'
Note
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1
2
3
4
5
6
7
8
To optimize instruction execution
(FASTREAD, DOFR,DIOFR,QOFR,
QIOFR, ROTP) according to the frequency
Dummy clock
cycle
VCR<7:4>
9
10
11
12
13
14
Target on maximum
allowed frequency fc
(108MHz) and to
1111
guarantee backward
compatibility (default)
0
Ready to enter XIP mode To make the data on DQ0 during the first
dummy clock NOT “Don’t Care.” For
VCR<3>
XIP
devices with feature set digit equal to 2 or 4
in the part number (Basic XiP), this bit is
1
XIP disabled (default)
always Don't Care"
VCR<2:0>
Reserved
xxx
reserved
Fixed value = 000b
6.3.1
Dummy clock cycle Volatile Configurations bits (VCR bits from 7 to 4)
The bits from 7 to 4 of the Volatile Configuration Register, as the bits from 15 to 12 of the
Volatile Configuration register, set the dummy clock cycles number after the fast read
instructions (in all the 3 available protocols). The dummy clock cycles number can be set
from 1 up to 15 as described in Table 6.: Volatile Configuration Register, according to
operating frequency (the higher is the operating frequency, the bigger must be the dummy
clock cycle number, according to Table 5.: Maximum allowed frequency (MHz)) to optimize
the fast read instructions performance.
Note:
If the dummy clock number is not sufficient for the operating frequency, the memory reads
wrong data.
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