Volatile and Non Volatile Registers
N25Q128 - 1.8 V
Table 7.
Bit
Volatile Enhanced Configuration Register
Parameter
Value
Description
Enabled
Note
0
VECR<7>
Quad Input Command
Enable command on four input lines
1
0
1
x
0
1
0
Disabled (default)
Enabled
VECR<6>
VECR<5>
VECR<4>
Dual Input Command
Reserved
Enable command on two input lines
Fixed value = 0b
Disabled (default)
Reserved
Disabled
Reset/Hold disable
Disable Pad Hold/Reset functionality
Enabled (default)
Enabled
Accelerator pin enable in
QIO-SPI protocol or in
QIFP/QIEFP
The bit must be considered in case of
QIFP, QIEFP, or QIO-SPI protocol. It is
“Don’t Care” otherwise.
VECR<3>
1
Disabled (default)
000
001
010
011
100
101
110
111
reserved
90
60
45
VECR<2:0> Output Driver Strength
Impedance at VCC/2
reserved
20
15
30 (default)
6.4.1
Quad Input Command VECR<7>
The Quad Input Command configuration bit can be used to make the memory start working
in QIO-SPI protocol directly after the Write Volatile Enhanced Configuration Register
(WRVECR) instruction. The default value of this bit is 1, corresponding to Extended SPI
protocol, If this bit is set to 0 the memory works in QIO-SPI protocol. If VECR bit 7 is set
back to 1 the memory start working again in Extended SPI protocol, unless the bit 6 is set to
0 (in this case the memory start working in DIO-SPI mode).
Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 7and bit 6 of the
VECR set to 0), the memory will work in QIO-SPI.
6.4.2
Dual Input Command VECR<6>
The Dual Input Command configuration bit can be used to make the memory start working
in DIO-SPI protocol directly after the Write Volatile Enhanced Configuration Register
(WVECR) instruction. The default value of this bit is 1, corresponding to Extended SPI
protocol, if this bit is set to 0 the memory works in DIO-SPI protocol (unless the Volatile
Enhanced Configuration Register bit 7 is also set to 0). If the Volatile Enhanced
Configuration Register bit 6 is set back to 1 the memory start working again in Extended SPI
protocol.
Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 7 and bit 6 of the
VECR are set to 0), the memory will work in QIO-SPI.
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