N25Q128 - 1.8 V
Volatile and Non Volatile Registers
Table 4.
Bit
Non-Volatile Configuration Register
Parameter
Value
111
Description
30 (default)
Note
0
1
Enabled
POR phase < 100us only read available
Fast POR x
READ
NVCR<5>
POR phase ~ 700us all instructions
available
Disabled (default)
0
disabled
Reset/Hold
disable
NVCR<4>
NVCR<3>
Disable Pad Hold/Reset functionality
Enable command on four input line
1
enabled (default)
enabled
0
Quad Input
Command
1
disabled (default)
enabled
0
Dual Input
Command
NVCR<2>
Enable command on two input line
Default value = "11"
1
disabled (default)
Don't care
NVCR<1:0>
Reserved
xx
6.2.1
Dummy clock cycle NV configuration bits (NVCR bits from 15 to 12)
The bits from 15 to 12 of the Non Volatile Configuration register store the default settings for
the dummy clock cycles number after the fast read instructions (in all the 3 available
protocols). The dummy clock cycles number can be set from 1 up to 15 as described here,
according to operating frequency (the higher is the operating frequency, the bigger must be
the dummy clock cycle number) to optimize the fast read instructions performance.
The default values of these bits allow the memory to be safely used with fast read
instructions at the maximum frequency (108 MHz). Please note that if the dummy clock
number is not sufficient for the operating frequency, the memory reads wrong data.
Table 5.
Maximum allowed frequency (MHz)
Maximum allowed frequency (MHz)(1)
Dummy Clock
FASTREAD
DOFR
DIOFR
QOFR
QIOFR
1
2
50
50
85
39
59
43
56
20
39
95
3
105
108
108
108
108
108
108
108
95
75
70
49
4
105
108
108
108
108
108
108
88
83
59
5
94
94
69
6
105
108
108
108
108
105
108
108
108
108
78
7
86
8
95
9
105
108
10
1. All values are guaranteed by characterization and not 100% tested in production.
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MICRON [ MICRON TECHNOLOGY ]
