N25Q128 - 1.8 V
XIP Operations
Table 25. NVCR XIP bits setting example
B1h
(WRNVCR
opcode)
+ 0110
100
111
0
1
11
xx
6 dummy cycles
for fast read
instructions
XIP set as
default; Quad
I/O mode
Output Buffer
driver strength
default
FAST POR
enabled
Hold/Reset
not disabled
Extended
SPI protocol
Don’t
Care
Figure 103. XIP mode directly after power on
NVCR check: XIP enabled
Vd
S
tVSI (<100μ)
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12
13
14 15 16
C
IO switches from Input to Output
DQ0
DQ1
DQ2
4
0
4
0
4
0
4
0
4
4
0
Xb
5
6
1
2
5
6
1
2
5
1
2
5
6
1
2
5
6
5
6
1
2
6
DQ3
7
3
7
3
7
3
7
3
7
3
7
A7-0
Dummy (ex.: 6)
Byte 1 Byte 2
A15-8
A23-16
Quad_XIP_After_Power-On
Note:
Xb is the XIP Confirmation bit, and it should be set to '0' to keep XIP state or '1' to exit XIP
mode and return to standard read mode.
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