XIP Operations
N25Q128 - 1.8 V
Figure 102. N25Q128 Read functionality Flow Chart
Power On
NVCR Check
No SPI standard mode (no
XiP, VCR <3> = 1)
SPI mode (no XIP) but
ready to enter XIP
Is XIP enabled ?
Yes
VCR<3> = 0 ?
No
Yes
No
XIP mode
Read Instructions ?
Yes
No
Yes
XiP Confirmation
bit = 0 ?
No
XiP Confirmation
bit = 0 ?
Yes
10.1
Enter XIP mode by setting the Non Volatile Configuration
Register
To use the Non Volatile Configuration Register method to enter in XIP mode it is necessary
to set the Non Volatile Configuration Register bits from 11 to 9 with the pattern
corresponding to the required XIP mode by mean of the Write Non Volatile Configuration
Register (WRNVCR) instruction. (See Table 25.: NVCR XIP bits setting example.)
This instruction doesn't affect the XIP state until the next Power on sequence. In this case,
after the next power on sequence, the memory directly accept addresses and then, after the
dummy clock cycles (configurable), outputs the data as described in Table 25.: NVCR XIP
bits setting example. For example to enable fast POR and XIP on QIOFR in normal SPI
protocol with six dummy clock cycles the following pattern must be issued:
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MICRON [ MICRON TECHNOLOGY ]
