Instructions
N25Q128 - 1.8 V
Table 20. Protection modes
Memory content
Protected area (1) Unprotected area (1)
W / VPP SRWD
Mode
Write protection of the status
register
Signal
bit
1
0
0
Status register is writeable, if the
WREN instruction has set the WEL
bit.
Protected against PP, Ready to accept PP,
DIFP, DIEFP, QIFP, DIFP, DIEFP, QIFP,
QIEFP, SSE, SE and QIEFP, SSE, and SE
0
Software
protected
(SPM)
The values in the SRWD, TB, BP3,
BP2, BP1, and BP0 bits can be
changed.
BE instructions.
instructions.
1
1
1
Status Register is hardware write
protected. The values in the
SRWD, TB, BP3, BP2, BP1 and
BP0 bits cannot be changed
PP, DIFP, DIEFP,
QIFP, QIEFP, SSE,
SE and BE
Hardware
protected
(HPM)
PP, DIFP, DIEFP,
QIFP, QIEFP, SSE,
and SE instructions.
0
instructions.
1. As defined by the values in the Block Protect (TB, BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 3:
Status register format.
9.1.24
Read Lock Register (RDLR)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Lock Register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any
location inside the concerned sector. Each address bit is latched-in during the rising edge of
Serial Clock (C). Then the value of the Lock Register is shifted out on Serial Data output
(DQ1), each bit being shifted out, at a maximum frequency fC, during the falling edge of
Serial Clock (C).
The Read Lock Register (RDLR) instruction is terminated by driving Chip Select (S) High at
any time during data output.
Any Read Lock Register (RDLR) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 32. Read Lock Register instruction and data-out sequence
S
C
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
Instruction
24-bit address
23 22 21
MSB
3
2
1
0
DQ0
DQ1
Lock register out
High Impedance
2
7
6
5
4
3
1
0
MSB
AI13738
104/185
MICRON [ MICRON TECHNOLOGY ]
