2Mb : 128K x 18, 64K x 32/36
FLOW-THROUGH SYNCBURST SRAM
READ/WRITE TIMING
t
KC
CLK
t
t
KL
KH
t
t
ADSH
ADSS
ADSP#
ADSC#
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WH
WS
BWE#,
BWa#-BWd#
(NOTE 4)
t
t
CEH
CES
CE#
(NOTE 2)
ADV#
OE#
t
t
DH
DS
t
OELZ
t
D
Q
High-Z
D(A3)
D(A5)
D(A6)
t
OEHZ
KQ
(NOTE 1)
Q(A4+1)
Q(A1)
Q(A2)
Q(A4)
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
Back-to-Back READs
Single WRITE
BURST READ
DONÕT CARE
UNDEFINED
READ/WRITE TIMING PARAMETERS
-6.8
-7.5
-8.5
-10
-6.8
-7.5
-8.5
-10
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
t
KC
8.0
8.8
10.0
15
ns
MHz
ns
WS
DS
1.8
1.8
1.8
0.5
0.5
0.5
0.5
0.5
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
KF
125
113
100
66
KH
1.8
1.8
1.9
1.9
1.9
1.9
4.0
4.0
CES
AH
KL
ns
KQ
6.8
3.8
7.5
4.2
8.5
5.0
10.0
5.0
ns
ADSH
WH
DH
OELZ
OEHZ
AS
0
0
0
0
ns
ns
1.8
1.8
2.0
2.0
2.0
2.0
2.5
2.5
ns
CEH
ADSS
ns
NOTE: 1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed.
4. GW# is HIGH.
5. Back-to-back READs may be controlled by either ADSP# or ADSC#.
2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM
MT58L128L18F_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
21
MICRON [ MICRON TECHNOLOGY ]
