2Mb : 128K x 18, 64K x 32/36
FLOW-THROUGH SYNCBURST SRAM
WRITE TIMING
t
KC
CLK
t
t
KL
KH
t
t
ADSH
ADSS
ADSP#
ADSC# extends burst.
t
t
t
t
ADSH
ADSS
ADSH
ADSS
ADSC#
t
t
AH
AS
A1
A2
A3
ADDRESS
BYTE WRITE signals are
ignored when ADSP# is LOW.
t
t
WH
WS
BWE#,
BWa#-BWd#
t
t
WH
(NOTE 5)
WS
GW#
t
t
CEH
CES
CE#
(NOTE 2)
t
t
AAH
AAS
ADV#
OE#
ADV# suspends burst.
(NOTE 4)
(NOTE 3)
t
t
DH
DS
D
Q
D(A2)
D(A2 + 1)
(NOTE 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
t
OEHZ
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DONÕT CARE UNDEFINED
WRITE TIMING PARAMETERS
-6.8
-7.5
-8.5
-10
-6.8
-7.5
-8.5
-10
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
t
KC
8.0
8.8
10.0
15
ns
MHz
ns
DS
1.8
1.8
0.5
0.5
0.5
0.5
0.5
0.5
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
KF
125
3.8
113
4.2
100
5.0
66
CES
AH
KH
1.8
1.8
1.9
1.9
1.9
1.9
4.0
4.0
KL
ns
ADSH
AAH
WH
DH
OEHZ
AS
5.0
ns
1.8
1.8
1.8
1.8
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.5
2.5
2.5
2.5
ns
ADSS
AAS
WS
ns
ns
CEH
ns
NOTE: 1. D(A2) refers to input for address A2. D(A2 + 1) refers to input for the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/
output data contention for the time period prior to the byte write enable inputs being sampled.
4. ADV# must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for the x18 version;
or GW# HIGH and BWE#, BWa#-BWd# LOW for the x32 and x36 versions.
2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM
MT58L128L18F_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
20