256Mb: x4, x8, x16 SDRAM
Functional Block Diagrams
Figure 2: 32 Meg x 8 Functional Block Diagram
CKE
CLK
CONTROL
LOGIC
CS#
WE#
BANK3
CAS#
RAS#
BANK2
BANK1
REFRESH
COUNTER
13
MODE REGISTER
12
BANK0
ROW-
ADDRESS
LATCH
&
ROW-
ADDRESS
MUX
13
BANK0
MEMORY
ARRAY
1
1
8192
DQM
13
(8192 x 1024 x 8)
DECODER
DATA
OUTPUT
REGISTER
SENSE AMPLIFIERS
8192
8
I/O GATING
2
8
DQ[7:0]
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
BANK
CONTROL
LOGIC
A[12:0]
BA[1:0]
ADDRESS
REGISTER
15
DATA
INPUT
REGISTER
2
8
1024
(x8)
COLUMN
DECODER
COLUMN-
ADDRESS
COUNTER/
LATCH
10
10
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. R 10/12 EN
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