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MT48LC64M4A2FB1 参数 Datasheet PDF下载

MT48LC64M4A2FB1图片预览
型号: MT48LC64M4A2FB1
PDF下载: 下载PDF文件 查看货源
内容描述: SDR SDRAM [SDR SDRAM]
分类和应用: 动态存储器
文件页数/大小: 86 页 / 3693 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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256Mb: x4, x8, x16 SDRAM  
General Description  
General Description  
The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory contain-  
ing 268,435,456 bits. It is internally configured as a quad-bank DRAM with a synchro-  
nous interface (all signals are registered on the positive edge of the clock signal, CLK).  
Each of the x4’s 67,108,864-bit banks is organized as 8192 rows by 2048 columns by 4  
bits. Each of the x8’s 67,108,864-bit banks is organized as 8192 rows by 1024 columns by  
8 bits. Each of the x16’s 67,108,864-bit banks is organized as 8192 rows by 512 columns  
by 16 bits.  
Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected  
location and continue for a programmed number of locations in a programmed se-  
quence. Accesses begin with the registration of an ACTIVE command, which is then fol-  
lowed by a READ or WRITE command. The address bits registered coincident with the  
ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the  
bank; A[12:0] select the row). The address bits registered coincident with the READ or  
WRITE command are used to select the starting column location for the burst access.  
The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8  
locations, or the full page, with a burst terminate option. An auto precharge function  
may be enabled to provide a self-timed row precharge that is initiated at the end of the  
burst sequence.  
The 256Mb SDRAM uses an internal pipelined architecture to achieve high-speed oper-  
ation. This architecture is compatible with the 2n rule of prefetch architectures, but it  
also allows the column address to be changed on every clock cycle to achieve a high-  
speed, fully random access. Precharging one bank while accessing one of the other  
three banks will hide the PRECHARGE cycles and provide seamless, high-speed, ran-  
dom-access operation.  
The 256Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh  
mode is provided, along with a power-saving, power-down mode. All inputs and out-  
puts are LVTTL-compatible.  
SDRAMs offer substantial advances in DRAM operating performance, including the  
ability to synchronously burst data at a high data rate with automatic column-address  
generation, the ability to interleave between internal banks to hide precharge time, and  
the capability to randomly change column addresses on each clock cycle during a burst  
access.  
Automotive Temperature  
The automotive temperature (AT) option adheres to the following specifications:  
• 16ms refresh rate  
• Self refresh not supported  
• Ambient and case temperature cannot be less than –40°C or greater than +105°C  
PDF: 09005aef8091e6d1  
256Mb_sdr.pdf - Rev. R 10/12 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
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© 1999 Micron Technology, Inc. All rights reserved.