256Mb: x4, x8, x16 SDRAM
Clock Suspend
Figure 57: Clock Suspend Mode
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CKS CKH
t
t
CMS
CMH
Command
DQM
READ
NOP
NOP
NOP
NOP
NOP
WRITE
NOP
t
t
CMS
CMH
t
t
AH
AS
Column e
Column m
Address
t
t
AH
AS
A10
t
t
AS
AH
BA0, BA1
Bank
Bank
t
AC
t
t
t
t
t
DH
OH
HZ
DS
AC
D
D
D
D
DQ
OUT
OUT
IN
IN
t
LZ
Don’t Care
Undefined
1. For this example, BL = 2, CL = 3, and auto precharge is disabled.
Note:
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This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. R 10/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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