256Mb: x4, x8, x16 SDRAM
Power-Down
Power-Down
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND IN-
HIBIT when no accesses are in progress. If power-down occurs when all banks are idle,
this mode is referred to as precharge power-down; if power-down occurs when there is a
row active in any bank, this mode is referred to as active power-down. Entering power-
down deactivates the input and output buffers, excluding CKE, for maximum power
savings while in standby. The device cannot remain in the power-down state longer
than the refresh period (64ms) because no REFRESH operations are performed in this
mode.
The power-down state is exited by registering a NOP or COMMAND INHIBIT with CKE
HIGH at the desired clock edge (meeting tCKS).
Figure 54: Power-Down Mode
T0
T1
T2
Tn + 1
Tn + 2
( (
) )
( (
) )
t
t
CK
CL
CLK
CKE
t
CH
t
t
CKS
CKS
( (
) )
t
t
CKS
CKH
t
t
CMS CMH
PRECHARGE
( (
) )
( (
) )
Command
DQM
NOP
NOP
NOP
ACTIVE
( (
) )
( (
) )
( (
) )
( (
) )
Address
A10
Row
Row
All banks
( (
) )
( (
) )
Single bank
t
t
AH
AS
( (
) )
( (
) )
BA0, BA1
DQ
Bank(s)
Bank
High-Z
( (
) )
Input buffers gated off
while in power-down mode
Two clock cycles
All banks idle
Precharge all
active banks
All banks idle, enter
power-down mode
Exit power-down mode
Don’t Care
1. Violating refresh requirements during power-down may result in a loss of data.
Note:
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. R 10/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
83
© 1999 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
