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MT48LC4M16A2P-75G 参数 Datasheet PDF下载

MT48LC4M16A2P-75G图片预览
型号: MT48LC4M16A2P-75G
PDF下载: 下载PDF文件 查看货源
内容描述: SDR SDRAM MT48LC16M4A2 â ????梅格4 ×4× 4银行MT48LC8M8A2 â ???? 2梅格×8× 4银行MT48LC4M16A2 â ???? 1梅格×16× 4银行 [SDR SDRAM MT48LC16M4A2 – 4 Meg x 4 x 4 Banks MT48LC8M8A2 – 2 Meg x 8 x 4 Banks MT48LC4M16A2 – 1 Meg x 16 x 4 Banks]
分类和应用: 动态存储器
文件页数/大小: 83 页 / 3595 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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64Mb: x4, x8, x16 SDRAM  
Clock Suspend  
Clock Suspend  
The clock suspend mode occurs when a column access/burst is in progress and CKE is  
registered LOW. In the clock suspend mode, the internal clock is deactivated, freezing  
the synchronous logic.  
For each positive clock edge on which CKE is sampled LOW, the next internal positive  
clock edge is suspended. Any command or data present on the input balls when an in-  
ternal clock edge is suspended will be ignored; any data present on the DQ balls re-  
mains driven; and burst counters are not incremented, as long as the clock is suspen-  
ded.  
Exit clock suspend mode by registering CKE HIGH; the internal clock and related opera-  
tion will resume on the subsequent positive clock edge.  
Figure 51: Clock Suspend During WRITE Burst  
T0  
T1  
T2  
T3  
T4  
T5  
CLK  
CKE  
Internal  
clock  
NOP  
WRITE  
NOP  
NOP  
Command  
Address  
DIN  
Bank,  
Col n  
D
D
D
IN  
IN  
IN  
Don’t Care  
1. For this example, BL = 4 or greater, and DQM is LOW.  
Note:  
PDF: 09005aef80725c0b  
64mb_x4x8x16_sdram.pdf - Rev. U 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
© 1999 Micron Technology, Inc. All rights reserved.  
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