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MT48LC4M16A2P-75G 参数 Datasheet PDF下载

MT48LC4M16A2P-75G图片预览
型号: MT48LC4M16A2P-75G
PDF下载: 下载PDF文件 查看货源
内容描述: SDR SDRAM MT48LC16M4A2 â ????梅格4 ×4× 4银行MT48LC8M8A2 â ???? 2梅格×8× 4银行MT48LC4M16A2 â ???? 1梅格×16× 4银行 [SDR SDRAM MT48LC16M4A2 – 4 Meg x 4 x 4 Banks MT48LC8M8A2 – 2 Meg x 8 x 4 Banks MT48LC4M16A2 – 1 Meg x 16 x 4 Banks]
分类和应用: 动态存储器
文件页数/大小: 83 页 / 3595 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号MT48LC4M16A2P-75G的Datasheet PDF文件第75页浏览型号MT48LC4M16A2P-75G的Datasheet PDF文件第76页浏览型号MT48LC4M16A2P-75G的Datasheet PDF文件第77页浏览型号MT48LC4M16A2P-75G的Datasheet PDF文件第78页浏览型号MT48LC4M16A2P-75G的Datasheet PDF文件第79页浏览型号MT48LC4M16A2P-75G的Datasheet PDF文件第81页浏览型号MT48LC4M16A2P-75G的Datasheet PDF文件第82页浏览型号MT48LC4M16A2P-75G的Datasheet PDF文件第83页  
64Mb: x4, x8, x16 SDRAM  
Power-Down  
Power-Down  
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND IN-  
HIBIT when no accesses are in progress. If power-down occurs when all banks are idle,  
this mode is referred to as precharge power-down; if power-down occurs when there is a  
row active in any bank, this mode is referred to as active power-down. Entering power-  
down deactivates the input and output buffers, excluding CKE, for maximum power  
savings while in standby. The device cannot remain in the power-down state longer  
than the refresh period (64ms) because no REFRESH operations are performed in this  
mode.  
The power-down state is exited by registering a NOP or COMMAND INHIBIT with CKE  
HIGH at the desired clock edge (meeting tCKS).  
Figure 50: Power-Down Mode  
T0  
T1  
T2  
Tn + 1  
Tn + 2  
( (  
) )  
( (  
) )  
t
t
CK  
CL  
CLK  
CKE  
t
CH  
t
t
CKS  
CKS  
( (  
) )  
t
t
CKS  
CKH  
t
t
CMS CMH  
PRECHARGE  
( (  
) )  
( (  
) )  
Command  
DQM  
NOP  
NOP  
NOP  
ACTIVE  
( (  
) )  
( (  
) )  
( (  
) )  
( (  
) )  
Address  
A10  
Row  
Row  
All banks  
( (  
) )  
( (  
) )  
Single bank  
t
t
AH  
AS  
( (  
) )  
( (  
) )  
BA0, BA1  
DQ  
Bank(s)  
Bank  
High-Z  
( (  
) )  
Input buffers gated off  
while in power-down mode  
Two clock cycles  
All banks idle  
Precharge all  
active banks  
All banks idle, enter  
power-down mode  
Exit power-down mode  
Don’t Care  
1. Violating refresh requirements during power-down may result in a loss of data.  
Note:  
PDF: 09005aef80725c0b  
64mb_x4x8x16_sdram.pdf - Rev. U 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
80  
© 1999 Micron Technology, Inc. All rights reserved.