128Mb: x4, x8, x16
SDRAM
WRITE – FULL-PAGE BURST
T0
T1
T2
T3
T4
T5
Tn + 1
Tn + 2
Tn + 3
( (
) )
( (
) )
t
t
CK
CL
CLK
t
CH
t
t
CKS
CKH
( (
) )
CKE
( (
) )
t
t
CMS
CMH
( (
) )
( (
) )
COMMAND
ACTIVE
NOP
WRITE
t
NOP
NOP
NOP
NOP
BURST TERM
NOP
t
CMH
CMS
( (
) )
DQM /
DQML, DQMH
( (
) )
t
t
AH
AS
( (
) )
( (
) )
1
A0-A9, A11
ROW
COLUMN m
t
t
AH
AS
( (
) )
( (
) )
ROW
A10
t
t
AH
AS
( (
) )
( (
) )
BA0, BA1
BANK
BANK
t
t
t
t
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
( (
) )
D
IN
m
D
IN m + 1
D
IN m + 2
D
IN m + 3
DIN m - 1
DQ
( (
) )
t
RCD
Full-page burst does not
self-terminate. Can use
BURST TERMINATE
512 (x16) locations within same row
1,024 (x8) locations within same row
2,048 (x4) locations within same row
command to stop.2, 3
Full page completed
DON’T CARE
TIMING PARAMETERS
-7E
-75
MAX
-8E
-7E
-75
MAX
-8E
SYMBOL* MIN
MAX
MIN
0.8
1.5
2.5
2.5
7.5
10
MIN
1
MAX UNITS
SYMBOL* MIN
MAX
MIN
1.5
0.8
1.5
0.8
1.5
20
MIN
2
MAX UNITS
t
t
AH
0.8
1.5
2.5
2.5
7
ns
ns
ns
ns
ns
ns
ns
CKS
CMH
CMS
DH
1.5
0.8
1.5
0.8
1.5
15
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
AS
2
1
CH
3
2
CL
3
1
CK (3)
CK (2)
CKH
8
DS
2
7.5
0.8
10
1
RCD
20
0.8
*CAS latency indicated in parentheses.
NOTE: 1. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
t
2. WR must be satisfied prior to PRECHARGE command.
3. Page left open; no tRP.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
54
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