128Mb: x4, x8, x16
SDRAM
1
WRITE – WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
t
CMS
CMH
DQM /
DQML, DQMH
t
t
AS
AH
2
A0-A9, A11
ROW
ROW
ROW
BANK
COLUMN m
t
t
AH
AS
ENABLE AUTO PRECHARGE
ROW
t
A10
t
AS
AH
BA0, BA1
BANK
BANK
t
t
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DS
DH
DIN
m
DIN m + 1
DIN m + 2
DIN m + 3
DQ
t
t
RP
t
RCD
WR
t
RAS
t
RC
DON’T CARE
TIMING PARAMETERS
-7E
-75
MAX
-8E
-7E
-75
MAX
-8E
SYMBOL* MIN
MAX
MIN
0.8
1.5
2.5
2.5
7.5
10
MIN
1
MAX UNITS
SYMBOL* MIN
MAX
MIN
1.5
MIN
MAX UNITS
t
t
AH
0.8
1.5
2.5
2.5
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMS
DH
DS
1.5
0.8
2
1
ns
ns
ns
ns
ns
ns
ns
–
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AS
2
0.8
CH
3
1.5
1.5
2
CL
3
RAS
RC
37
120,000
44
120,000
50
120,000
CK (3)
CK (2)
CKH
CKS
CMH
8
60
66
70
7.5
0.8
1.5
0.8
10
1
RCD
RP
15
20
20
0.8
1.5
0.8
15
20
20
2
WR
1 CLK +
7ns
1 CLK +
7.5ns
1 CLK +
7ns
1
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
50
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