128Mb: x4, x8, x16
SDRAM
1
ALTERNATING BANK WRITE ACCESSES
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
ACTIVE
NOP
WRITE
NOP
NOP
ACTIVE
t
t
CMS
CMH
DQM /
DQML, DQMH
t
t
AH
AS
2
2
A0-A9, A11
ROW
ROW
ROW
ROW
ROW
COLUMN m
COLUMN b
t
t
AH
AS
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
A10
t
t
AH
AS
BA0, BA1
BANK 0
BANK 0
BANK 1
t
BANK 1
BANK 0
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DS
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
DH
DIN
m
DIN m + 1
DIN m + 2
DIN m + 3
DIN
b
DIN b + 1
DIN b + 2
DIN b + 3
DQ
t
t
t
t
RCD - BANK 0
WR - BANK 0
RP - BANK 0
RCD - BANK 0
t
RAS - BANK 0
t
RC - BANK 0
t
t
WR - BANK 1
t
RCD - BANK 1
RRD
DON’T CARE
TIMING PARAMETERS
-7E
-75
MAX
-8E
-7E
MAX
-75
-8E
SYMBOL* MIN
MAX
MIN
0.8
1.5
2.5
2.5
7.5
10
MIN
MAX UNITS
SYMBOL* MIN
MIN
0.8
MAX
MIN
1
MAX UNITS
t
t
t
t
t
t
t
t
t
AH
0.8
1.5
2.5
2.5
7
1
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DH
DS
0.8
1.5
ns
ns
t
t
t
t
t
t
t
t
t
AS
1.5
2
CH
3
RAS
RC
37
120,000
44
120,000
50
70
20
20
20
120,000
ns
ns
ns
ns
ns
–
CL
3
60
66
CK (3)
CK (2)
CKH
CKS
CMH
CMS
8
RCD
RP
15
20
7.5
0.8
1.5
0.8
1.5
10
1
15
20
0.8
1.5
0.8
1.5
RRD
WR
14
15
2
1 CLK +
7ns
1 CLK +
7.5ns
1 CLK +
7ns
1
2
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
53
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