128Mb: x4, x8, x16
SDRAM
1
READ – FULL-PAGE BURST
T0
T1
T2
T3
T4
T5
T6
Tn + 1
Tn + 2
Tn + 3
Tn + 4
( (
) )
( (
) )
t
t
CK
CL
CLK
t
CH
t
t
CKS
CKH
( (
) )
CKE
( (
) )
t
t
CMS
CMH
( (
) )
( (
) )
COMMAND
ACTIVE
NOP
READ
t
NOP
NOP
NOP
NOP
NOP
BURST TERM
NOP
NOP
t
CMS
CMH
( (
) )
DQM /
DQML, DQMH
( (
) )
t
t
AH
AS
( (
) )
( (
) )
2
A0-A9, A11
ROW
COLUMN m
t
t
AH
AS
( (
) )
( (
) )
ROW
A10
t
t
AH
AS
( (
) )
( (
) )
BA0, BA1
BANK
BANK
t
t
t
t
t
AC
AC
AC
AC
AC
( (
) )
t
t
t
t
t
t
t
OH
AC
OH
OH
OH
OH
OH
( (
) )
( (
) )
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m-1
D
OUT
m
DOUT m+1
DQ
t
LZ
t
HZ
512 (x16) locations within same row
1,024 (x8) locations within same row
2,048 (x4) locations within same row
t
RCD
CAS Latency
Full page completed
DON’T CARE
Full-page burst does not self-terminate.
Can use BURST TERMINATE command.
3
UNDEFINED
TIMING PARAMETERS
-7E
-75
MAX
-8E
-7E
-75
-8E
SYMBOL* MNI
MAX
5.4
MIN
MIN
MAX UNITS
SYMBOL* MIN
MAX
MIN
1.5
MAX
MIN
MAX UNITS
t
t
AC (3)
5.4
6
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
CKS
1.5
0.8
1.5
2
1
2
ns
ns
ns
t
t
t
t
t
t
t
t
AC (2)
5.4
CMH
CMS
HZ(3)
HZ(2)
LZ
0.8
t
AH
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
1
2
1.5
t
t
t
t
t
t
AS
5.4
5.4
5.4
6
6
6
ns
ns
ns
ns
ns
CH
3
CL
3
1
3
1
3
1
3
CK (3)
CK (2)
CKH
8
OH
7.5
0.8
10
1
RCD
15
20
20
0.8
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the CAS latency = 2.
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
3. Page left open; no tRP.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
47
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