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MT48LC8M16A2FB-8EL 参数 Datasheet PDF下载

MT48LC8M16A2FB-8EL图片预览
型号: MT48LC8M16A2FB-8EL
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM [SYNCHRONOUS DRAM]
分类和应用: 动态存储器
文件页数/大小: 59 页 / 1835 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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128Mb: x4, x8, x16  
SDRAM  
Fixed-length or full-page WRITE bursts can be trun-  
cated with the BURST TERMINATE command. When  
truncating a WRITE burst, the input data applied coinci-  
dent with the BURST TERMINATE command will be  
ignored. The last data written (provided that DQM is  
LOW at that time) will be the input data applied one clock  
previous to the BURST TERMINATE command. This is  
shown in Figure 19, where data n is the last desired data  
element of a longer burst.  
PRECHARGE  
The PRECHARGE command (see Figure 20) is used to  
deactivate the open row in a particular bank or the open  
row in all banks. The bank(s) will be available for a subse-  
quent row access some specified time (tRP) after the  
PRECHARGE command is issued. Input A10 determines  
whether one or all banks are to be precharged, and in the  
case where only one bank is to be precharged, inputs  
BA0, BA1 select the bank. When all banks are to be  
precharged, inputs BA0, BA1 are treated as “Don’t Care.”  
Once a bank has been precharged, it is in the idle state  
and must be activated prior to any READ or WRITE com-  
mands being issued to that bank.  
T0  
T1  
T2  
CLK  
POWER-DOWN  
Power-down occurs if CKE is registered LOW coinci-  
dent with a NOP or COMMAND INHIBIT when no ac-  
cesses are in progress. If power-down occurs when all  
banks are idle, this mode is referred to as precharge  
power-down; if power-down occurs when there is a row  
active in any bank, this mode is referred to as active  
power-down. Entering power-down deactivates the in-  
put and output buffers, excluding CKE, for maximum  
power savings while in standby. The device may not  
remain in the power-down state longer than the refresh  
period (64ms) since no refresh operations are performed  
in this mode.  
BURST  
TERMINATE  
NEXT  
COMMAND  
WRITE  
COMMAND  
ADDRESS  
DQ  
BANK,  
COL n  
(ADDRESS)  
(DATA)  
DIN  
n
The power-down state is exited by registering a NOP  
or COMMAND INHIBIT and CKE HIGH at the desired  
clock edge (meeting tCKS). See Figure 21.  
Figure 19  
Terminating a WRITE Burst  
CLK  
( (  
) )  
CLK  
( (  
) )  
CKE  
CS#  
HIGH  
> t  
CKS  
t
CKS  
CKE  
( (  
) )  
( (  
) )  
( (  
) )  
COMMAND  
NOP  
NOP  
ACTIVE  
RAS#  
t
All banks idle  
RCD  
Input buffers gated off  
t
RAS  
t
RC  
CAS#  
WE#  
Enter power-down mode.  
Exit power-down mode.  
DONT CARE  
Figure 21  
Power-Down  
A0-A9  
A10  
All Banks  
Bank Selected  
BANK  
ADDRESS  
BA0,1  
Figure 20  
PRECHARGE Command  
128Mb: x4, x8, x16 SDRAM  
128MSDRAM_E.p65 Rev. E; Pub. 1/02  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2001, Micron Technology, Inc.  
24  
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