128Mb: x4, x8, x16
SDRAM
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto
precharge): A READ to bank m will interrupt a WRITE
on bank n when registered, with the data-out appear-
ing CAS latency later. The PRECHARGE to bank n will
4. Interrupted by a WRITE (with or without auto
precharge):AWRITEto bankm willinterruptaWRITE
on bank n when registered. The PRECHARGE to bank
n will begin after tWR is met, where tWR begins when
t
t
begin after WR is met, where WR begins when the
READ to bank m is registered. The last valid WRITE to
bank n will be data-in registered one clock prior to the
READ to bank m (Figure 26).
the WRITE to bank
m
is registered.
The last valid data WRITE to bank n will be data
registered one clock prior to a WRITE to bank m
(Figure 27).
T0
T1
T2
T3
T4
T5
T6
T7
CLK
WRITE - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
BANK n
t
RP - BANK n
t
WR - BANK n
Internal
States
t
RP - BANK m
Page Active
READ with Burst of 4
BANK m
BANK n,
COL a
BANK m,
COL d
ADDRESS
DQ
D
IN
D
a + 1
IN
D
OUT
DOUT
d + 1
a
d
CAS Latency = 3 (BANK m)
NOTE: 1. DQM is LOW.
Figure 26
WRITE With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
WRITE - AP
BANK n
WRITE - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
BANK n
t
RP - BANK n
t
WR - BANK n
Internal
States
t
WR - BANK m
Write-Back
Page Active
WRITE with Burst of 4
BANK m
BANK n,
COL a
BANK m,
COL d
ADDRESS
DQ
DIN
D
a + 1
IN
D
a + 2
IN
DIN
D
d + 1
IN
D
d + 2
IN
DIN
d + 3
a
d
NOTE: 1. DQM is LOW.
DON’T CARE
Figure 27
WRITE With Auto Precharge Interrupted by a WRITE
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
27
MICRON [ MICRON TECHNOLOGY ]
