128Mb: x4, x8, x16
SDRAM
WRITEs
WRITE bursts are initiated with a WRITE command,
as shown in Figure 13.
command applies to the new command. An example is
shown in Figure 15. Data n + 1 is either the last of a burst
of two or the last desired of a longer burst. The 128Mb
SDRAM uses a pipelined architecture and therefore does
not require the 2n rule associated with a prefetch archi-
tecture. A WRITE command can be initiated on any clock
cycle following a previous WRITE command. Full-speed
random write accesses within a page can be performed to
thesamebank, asshowninFigure16, oreachsubsequent
WRITE may be performed to a different bank.
The starting column and bank addresses are pro-
vided with the WRITE command, and auto precharge is
either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric WRITE commands used in the following illustra-
tions, auto precharge is disabled.
During WRITE bursts, the first valid data-in element
will be registered coincident with the WRITE command.
Subsequent data elements will be registered on each
successive positive clock edge. Upon completion of a
fixed-length burst, assuming no other commands have
been initiated, the DQs will remain High-Z and any addi-
tional input data will be ignored (see Figure 14). A full-
page burst will continue until terminated. (At the end of
the page, it will wrap to column 0 and continue.)
Data for any WRITE burst may be truncated with a
subsequentWRITEcommand, anddataforafixed-length
WRITE burst may be immediately followed by data for a
WRITE command. The new WRITE command can be
issued on any clock following the previous WRITE com-
mand, and the data provided coincident with the new
T0
T1
T2
T3
CLK
WRITE
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
BANK,
COL n
D
IN
DIN
n + 1
n
NOTE:
Burst length = 2. DQM is LOW.
Figure 14
WRITE Burst
CLK
CKE
CS#
HIGH
T0
T1
T2
CLK
RAS#
WRITE
NOP
WRITE
COMMAND
ADDRESS
DQ
CAS#
WE#
BANK,
COL n
BANK,
COL b
A0-A9, A11: x4
A0-A9: x8
COLUMN
ADDRESS
A0-A8: x16
DIN
DIN
DIN
b
n
n + 1
A11: x8
A9, A11: x16
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
A10
NOTE:
DQM is LOW. Each WRITE
command may be to any bank.
DON’T CARE
BANK
ADDRESS
BA0,1
Figure 15
WRITE to WRITE
Figure 13
WRITE Command
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
22
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