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MT48LC2M32B2TG 参数 Datasheet PDF下载

MT48LC2M32B2TG图片预览
型号: MT48LC2M32B2TG
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM [SYNCHRONOUS DRAM]
分类和应用: 动态存储器
文件页数/大小: 53 页 / 1810 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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64Mb: x32  
SDRAM  
Fixed-length or full-page WRITE bursts can be trun-  
cated with the BURST TERMINATE command. When  
truncating a WRITE burst, the input data applied coin-  
cident with the BURST TERMINATE command will be  
ignored. The last data written (provided that DQM is  
LOW at that time) will be the input data applied one  
clock previous to the BURST TERMINATE command.  
This is shown in Figure 19, where data n is the last  
desired data element of a longer burst.  
PRECHARGE  
The PRECHARGE command (Figure 20) is used to  
deactivate the open row in a particular bank or the  
open row in all banks. The bank(s) will be available for  
a subsequent row access some specified time (tRP) af-  
ter the PRECHARGE command is issued. Input A10  
determines whether one or all banks are to be  
precharged, and in the case where only one bank is to  
be precharged, inputs BA0 and BA1 select the bank.  
When all banks are to be precharged, inputs BA0 and  
BA1 are treated as “Don’t Care.” Once a bank has been  
precharged, it is in the idle state and must be activated  
prior to any READ or WRITE commands being issued to  
that bank.  
Figure 19  
Terminating a WRITE Burst  
T0  
T1  
T2  
POWER-DOWN  
CLK  
Power-down occurs if CKE is registered LOW coinci-  
dent with a NOP or COMMAND INHIBIT when no ac-  
cesses are in progress (see Figure 21). If power-down  
occurs when all banks are idle, this mode is referred to  
as precharge power-down; if power-down occurs when  
there is a row active in either bank, this mode is referred  
to as active power-down. Entering power-down deacti-  
vates the input and output buffers, excluding CKE, for  
maximum power savings while in standby. The device  
may not remain in the power-down state longer than  
the refresh period (64ms) since no refresh operations  
are performed in this mode.  
BURST  
TERMINATE  
NEXT  
COMMAND  
WRITE  
COMMAND  
ADDRESS  
DQ  
BANK,  
COL n  
(ADDRESS)  
(DATA)  
DIN  
n
NOTE: DQMs are LOW.  
The power-down state is exited by registering a NOP  
or COMMAND INHIBIT and CKE HIGH at the desired  
t
clock edge (meeting CKS).  
Figure 20  
PRECHARGECommand  
Figure 21  
CLK  
Power-Down  
CKE  
CS#  
HIGH  
( (  
) )  
( (  
CLK  
) )  
> t  
CKS  
t
CKS  
CKE  
( (  
) )  
( (  
) )  
( (  
) )  
RAS#  
COMMAND  
NOP  
NOP  
ACTIVE  
t
All banks idle  
RCD  
CAS#  
WE#  
Input buffers gated off  
t
RAS  
t
RC  
Enter power-down mode.  
Exit power-down mode.  
DON’T CARE  
A0–A9  
A10  
All Banks  
Bank Selected  
BANK  
ADDRESS  
BA0, 1  
64Mb: x32 SDRAM  
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02  
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.  
©2002,MicronTechnology,Inc.  
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