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MT48LC2M32B2TG 参数 Datasheet PDF下载

MT48LC2M32B2TG图片预览
型号: MT48LC2M32B2TG
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM [SYNCHRONOUS DRAM]
分类和应用: 动态存储器
文件页数/大小: 53 页 / 1810 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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64Mb: x32  
SDRAM  
WRITEs  
WRITE bursts are initiated with a WRITE command,  
as shown in Figure 13.  
can be issued on any clock following the previous WRITE  
command, and the data provided coincident with the  
new command applies to the new command. An ex-  
ample is shown in Figure 15. Data n + 1 is either the last  
of a burst of two or the last desired of a longer burst.  
This 64Mb SDRAM uses a pipelined architecture and  
therefore does not require the 2n rule associated with a  
prefetch architecture. A WRITE command can be initi-  
ated on any clock cycle following a previous WRITE  
command. Full-speed random write accesses within a  
page can be performed to the same bank, as shown in  
Figure 16, or each subsequent WRITE may be per-  
formed to a different bank.  
The starting column and bank addresses are pro-  
vided with the WRITE command, and auto precharge  
is either enabled or disabled for that access. If auto  
precharge is enabled, the row being accessed is  
precharged at the completion of the burst. For the ge-  
neric WRITE commands used in the following  
illustrations,auto precharge is disabled.  
During WRITE bursts, the first valid data-in ele-  
ment will be registered coincident with the WRITE com-  
mand. Subsequent data elements will be registered on  
each successive positive clock edge. Upon completion  
of a fixed-length burst, assuming no other commands  
have been initiated, the DQs will remain High-Z and  
any additional input data will be ignored (see Figure  
14). A full-page burst will continue until terminated.  
(At the end of the page, it will wrap to column 0 and  
continue.)  
Figure 14  
WRITE Burst  
T0  
T1  
T2  
T3  
CLK  
Data for any WRITE burst may be truncated with a  
subsequent WRITE command, and data for a fixed-  
length WRITE burst may be immediately followed by  
data for a WRITE command. The new WRITE command  
WRITE  
NOP  
NOP  
NOP  
COMMAND  
ADDRESS  
DQ  
BANK,  
COL n  
Figure 13  
WRITE Command  
D
IN  
DIN  
n + 1  
n
CLK  
CKE HIGH  
Figure 15  
WRITE to WRITE  
CS#  
T0  
T1  
T2  
RAS#  
CLK  
CAS#  
WE#  
WRITE  
NOP  
WRITE  
COMMAND  
ADDRESS  
DQ  
BANK,  
COL n  
BANK,  
COL b  
COLUMN  
ADDRESS  
A0–A7  
A8, A9  
DIN  
DIN  
DIN  
b
n
n + 1  
ENABLE AUTO PRECHARGE  
DISABLE AUTO PRECHARGE  
A10  
DON’T CARE  
NOTE: DQM is LOW. Each WRITE command may  
be to any bank.  
BANK  
ADDRESS  
BA0, 1  
64Mb: x32 SDRAM  
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02  
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.  
©2002,MicronTechnology,Inc.  
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