64Mb: x32
SDRAM
Data for any WRITE burst may be truncated with a
subsequent READ command, and data for a fixed-
length WRITE burst may be immediately followed by a
READ command. Once the READ command is regis-
tered, the data inputs will be ignored, and WRITEs will
not be executed. An example is shown in Figure 17.
Data n + 1 is either the last of a burst of two or the last
desired of a longer burst.
Data for a fixed-length WRITE burst may be fol-
lowed by, or truncated with, a PRECHARGE command
to the same bank (provided that auto precharge was
not activated), and a full-page WRITE burst may be
truncated with a PRECHARGE command to the same
bank. The PRECHARGE command should be issued
tWR after the clock edge at which the last desired input
data element is registered. The “two-clock” write-back
requires at least one clock plus time, regardless of fre-
quency, in auto precharge mode. In addition, when
truncating a WRITE burst, the DQM signal must be
used to mask input data for the clock edge prior to, and
the clock edge coincident with, the PRECHARGE com-
mand. An example is shown in Figure 18. Data n + 1 is
either the last of a burst of two or the last desired of a
longer burst. Following the PRECHARGE command, a
subsequent command to the same bank cannot be
t
issued until RP is met. The precharge will actually be-
gin coincident with the clock-edge (T2 in Figure 18) on
t
a “one-clock” WR and sometime between the first and
second clock on a “two-clock” tWR (between T2 and T3
in Figure 18.)
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the com-
mand and address buses be available at the appropri-
ate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to trun-
cate fixed-length or full-page bursts.
Figure 16
Random WRITE Cycles
T0
T1
T2
T3
CLK
WRITE
WRITE
WRITE
WRITE
COMMAND
ADDRESS
DQ
Figure 18
WRITE to PRECHARGE
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
T0
T1
T2
T3
T4
T5
T6
D
IN
D
IN
D
IN
DIN
x
CLK
m
n
a
t
t
t
WR = 1 CLK ( CK > WR)
DON’T CARE
DQM
NOTE: Each WRITE command may be to any bank. DQM is LOW.
t
RP
NOP
NOP
NOP
WRITE
NOP
PRECHARGE
ACTIVE
COMMAND
ADDRESS
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
Figure 17
t
WR
WRITE to READ
D
n
IN
DIN
n + 1
DQ
T0
T1
T2
T3
T4
T5
t
t
t
CLK
WR = 2 CLK (when WR > CK)
DQM
WRITE
NOP
READ
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
t
RP
NOP
NOP
WRITE
NOP
NOP
PRECHARGE
ACTIVE
COMMAND
ADDRESS
BANK,
COL n
BANK,
COL b
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
t
WR
DIN
n
DIN
n + 1
DOUT
b
DOUT
b + 1
D
IN
DIN
n + 1
DQ
n
DON’T CARE
NOTE:
DQM could remain LOW in this example if the WRITE burst is a fixed
length of two.
DON’T CARE
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
20
MICRON [ MICRON TECHNOLOGY ]
