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MT47H128M8HV-187EAT 参数 Datasheet PDF下载

MT47H128M8HV-187EAT图片预览
型号: MT47H128M8HV-187EAT
PDF下载: 下载PDF文件 查看货源
内容描述: DDR2 SDRAM [DDR2 SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 131 页 / 9265 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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1Gb: x4, x8, x16 DDR2 SDRAM  
Input Slew Rate Derating  
Input Slew Rate Derating  
For all input signals, the total tIS (setup time) and tIH (hold time) required is calculated  
by adding the data sheet tIS (base) and tIH (base) value to the ΔtIS and ΔtIH derating  
value, respectively. Example: tIS (total setup time) = tIS (base) + ΔtIS.  
tIS, the nominal slew rate for a rising signal, is defined as the slew rate between the last  
crossing of VREF(DC) and the first crossing of VIH(AC)min. Setup nominal slew rate (tIS) for  
a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the  
first crossing of VIL(AC)max  
.
If the actual signal is always earlier than the nominal slew rate line between shaded  
“VREF(DC) to AC region,” use the nominal slew rate for the derating value (Figure 23  
(page 58)).  
If the actual signal is later than the nominal slew rate line anywhere between the sha-  
ded “VREF(DC) to AC region,” the slew rate of a tangent line to the actual signal from the  
AC level to DC level is used for the derating value (see Figure 24 (page 58)).  
tIH, the nominal slew rate for a rising signal, is defined as the slew rate between the last  
crossing of VIL(DC)max and the first crossing of VREF(DC). tIH, nominal slew rate for a fall-  
ing signal, is defined as the slew rate between the last crossing of VIH(DC)min and the first  
crossing of VREF(DC)  
.
If the actual signal is always later than the nominal slew rate line between shaded “DC  
to VREF(DC) region,” use the nominal slew rate for the derating value (Figure 25  
(page 59)).  
If the actual signal is earlier than the nominal slew rate line anywhere between shaded  
“DC to VREF(DC) region,” the slew rate of a tangent line to the actual signal from the DC  
level to VREF(DC) level is used for the derating value (Figure 26 (page 59)).  
Although the total setup time might be negative for slow slew rates (a valid input signal  
will not have reached VIH[AC]/VIL[AC] at the time of the rising clock transition), a valid  
input signal is still required to complete the transition and reach VIH(AC)/VIL(AC)  
.
For slew rates in between the values listed in Table 28 (page 56) and Table 29  
(page 57), the derating values may obtained by linear interpolation.  
PDF: 09005aef821ae8bf  
1GbDDR2.pdf – Rev. T 02/10 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
55  
© 2004 Micron Technology, Inc. All rights reserved.  
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