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MT41J256M4 参数 Datasheet PDF下载

MT41J256M4图片预览
型号: MT41J256M4
PDF下载: 下载PDF文件 查看货源
内容描述: DDR3 SDRAM MT41J256M4 â ????梅格32 ×4× 8银行MT41J128M8 â ????梅格16 ×8× 8银行MT41J64M16 â ???? 8梅格×16× 8银行 [DDR3 SDRAM MT41J256M4 – 32 Meg x 4 x 8 banks MT41J128M8 – 16 Meg x 8 x 8 banks MT41J64M16 – 8 Meg x 16 x 8 banks]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 214 页 / 2938 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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1Gb: x4, x8, x16 DDR3 SDRAM  
Command and Address Setup, Hold, and Derating  
Command and Address Setup, Hold, and Derating  
The total tIS (setup time) and tIH (hold time) required is calculated by adding the data  
sheet tIS (base) and tIH (base) values (see Table 58; values come from Table 56  
(page 09)) to the ΔtIS and ΔtIH derating values (see Table 59 (page 1±±) and Table 6±  
(page 1±±)), respectively. Example: tIS (total setup time) = tIS (base) + ΔtIS. For a valid  
transition, the input signal has to remain above/below VIH(AC)/VIL(AC) for some time  
tVAC (see Table 6± (page 1±±)).  
Although the total setup time for slow slew rates might be negative (for example, a valid  
input signal will not have reached VIH(AC)/VIL(AC) at the time of the rising clock transi-  
tion), a valid input signal is still required to complete the transition and to reach  
VIH(AC)/VIL(AC) (see Figure 15 (page 49) for input signal requirements). For slew rates that  
fall between the values listed in Table 6± (page 1±±) and Table 63 (page 1±2), the derat-  
ing values may be obtained by linear interpolation.  
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the  
last crossing of VREF(DC) and the first crossing of VIH(AC)min. Setup (tIS) nominal slew rate  
for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and  
the first crossing of VIL(AC)max. If the actual signal is always earlier than the nominal slew  
rate line between the shaded VREF(DC)-to-AC region, use the nominal slew rate for derat-  
ing value (see Figure 34 (page 1±3)). If the actual signal is later than the nominal slew  
rate line anywhere between the shaded VREF(DC)-to-AC region, the slew rate of a tangent  
line to the actual signal from the AC level to the DC level is used for derating value (see  
Figure 36 (page 1±5)).  
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the  
last crossing of VIL(DC)max and the first crossing of VREF(DC). Hold (tIH) nominal slew rate  
for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and  
the first crossing of VREF(DC). If the actual signal is always later than the nominal slew  
rate line between the shaded DC-to-VREF(DC) region, use the nominal slew rate for derat-  
ing value (see Figure 35 (page 1±4)). If the actual signal is earlier than the nominal slew  
rate line anywhere between the shaded DC-to-VREF(DC) region, the slew rate of a tangent  
line to the actual signal from the DC level to the VREF(DC) level is used for derating value  
(see Figure 30 (page 1±6)).  
Table 58: Command and Address Setup and Hold Values Referenced – AC/DC-Based  
Symbol  
800  
200  
350  
1066  
125  
275  
1333  
65  
1600  
45  
1866  
2133  
Unit  
ps  
Reference  
VIH(AC)/VIL(AC)  
VIH(AC)/VIL(AC)  
VIH(AC)/VIL(AC)  
VIH(AC)/VIL(AC)  
VIH(DC)/VIL(DC)  
tIS(base, AC175)  
tIS(base, AC150)  
tIS(base, AC135)  
tIS(base, AC125)  
tIH(base, DC100)  
190  
170  
ps  
65  
60  
ps  
150  
100  
135  
95  
ps  
275  
200  
140  
120  
ps  
PDF: 09005aef826aa906  
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
99  
‹ 2006 Micron Technology, Inc. All rights reserved.  
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