1Gb: x4, x8, x16 DDR3 SDRAM
Command and Address Setup, Hold, and Derating
Table 63: Minimum Required Time tVAC Above VIH(AC) or Below VIL(AC)for Valid Transition
Slew Rate (V/ns)
tVAC at 175mV (ps) tVAC at 150mV (ps)
tVAC at 135mV (ps)
tVAC at 125mV (ps)
>2.0
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
<0.5
75
57
175
170
168
168
145
100
85
173
173
152
110
96
50
167
38
130
34
113
29
93
66
79
22
66
42
56
Note 1
Note 1
Note 1
30
10
27
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
1. Rising input signal shall become equal to or greater than VIH(ac) level and Falling input
signal shall become equal to or less than VIL(ac) level.
Note:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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