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MT41J256M4 参数 Datasheet PDF下载

MT41J256M4图片预览
型号: MT41J256M4
PDF下载: 下载PDF文件 查看货源
内容描述: DDR3 SDRAM MT41J256M4 â ????梅格32 ×4× 8银行MT41J128M8 â ????梅格16 ×8× 8银行MT41J64M16 â ???? 8梅格×16× 8银行 [DDR3 SDRAM MT41J256M4 – 32 Meg x 4 x 8 banks MT41J128M8 – 16 Meg x 8 x 8 banks MT41J64M16 – 8 Meg x 16 x 8 banks]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 214 页 / 2938 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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Table 56: Electrical Characteristics and AC Operating Conditions (Continued)  
Notes 1–8 apply to the entire table  
DDR3-800  
Min Max  
DDR3-1066  
DDR3-1333  
DDR3-1600  
Parameter  
Symbol  
tQSH  
tQSL  
tLZDQS  
tHZDQS  
tRPRE  
Min  
0.38  
0.38  
–600  
Max  
Min  
0.40  
0.40  
–500  
Max  
Min  
0.40  
0.40  
–450  
Max  
Unit Notes  
DQS, DQS# differential output high time  
DQS, DQS# differential output low time  
DQS, DQS# Low-Z time (RL - 1)  
0.38  
0.38  
–800  
CK  
CK  
ps  
21  
21  
400  
300  
250  
225  
22, 23  
22, 23  
23, 24  
23, 27  
DQS, DQS# High-Z time (RL + BL/2)  
DQS, DQS# differential READ preamble  
DQS, DQS# differential READ postamble  
400  
300  
250  
225  
ps  
0.9  
Note 24  
Note 27  
0.9  
Note 24  
Note 27  
0.9  
Note 24  
Note 27  
0.9  
Note 24  
Note 27  
CK  
CK  
tRPST  
0.3  
0.3  
0.3  
0.3  
Command and Address Timing  
DLL locking time  
tDLLK  
tIS  
512  
200  
512  
125  
512  
65  
512  
45  
CK  
ps  
28  
CTRL, CMD, ADDR  
setup to CK,CK#  
Base (specification)  
29, 30,  
44  
(AC175)  
V
REF @ 1 V/ns  
375  
350  
300  
275  
240  
190  
220  
170  
ps  
ps  
20, 30  
CTRL, CMD, ADDR  
setup to CK,CK#  
Base (specification)  
tIS  
(AC150)  
29, 30,  
44  
V
REF @ 1 V/ns  
CTRL, CMD, ADDR hold Base (specification)  
from CK,CK#  
500  
275  
375  
900  
425  
200  
300  
780  
340  
140  
240  
620  
320  
120  
220  
560  
ps  
ps  
ps  
ps  
ns  
ns  
ns  
ns  
CK  
20, 30  
29, 30  
20, 30  
41  
tIH  
(DC100)  
V
REF @ 1 V/ns  
Minimum CTRL, CMD, ADDR pulse width  
ACTIVATE to internal READ or WRITE delay  
PRECHARGE command period  
tIPW  
tRCD  
tRP  
tRAS  
tRC  
See Speed Bin Tables (page 74) for tRCD  
See Speed Bin Tables (page 74) for tRP  
See Speed Bin Tables (page 74) for tRAS  
See Speed Bin Tables (page 74) for tRC  
31  
31  
ACTIVATE-to-PRECHARGE command period  
ACTIVATE-to-ACTIVATE command period  
ACTIVATE-to-ACTIVATE x4/x8 (1KB page  
31, 32  
31, 43  
31  
tRRD  
MIN = greater of MIN = greater of MIN = greater of MIN = greater of  
4CK or 10ns 4CK or 7.5ns 4CK or 6ns 4CK or 6ns  
MIN = greater of 4CK or 10ns MIN = greater of 4CK or 7.5ns  
minimum command  
period  
size)  
x16 (2KB page size)  
CK  
ns  
31  
31  
Four ACTIVATE  
windows  
x4/x8 (1KB page  
size)  
tFAW  
40  
37.5  
30  
30  
x16 (2KB page size)  
50  
50  
45  
40  
ns  
ns  
31  
Write recovery time  
tWR  
MIN = 15ns; MAX = n/a  
MIN = greater of 4CK or 7.5ns; MAX = n/a  
31, 32,  
33,34  
Delay from start of internal WRITE  
tWTR  
CK  
31, 34  
transaction to internal READ command  
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