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MT41J256M4 参数 Datasheet PDF下载

MT41J256M4图片预览
型号: MT41J256M4
PDF下载: 下载PDF文件 查看货源
内容描述: DDR3 SDRAM MT41J256M4 â ????梅格32 ×4× 8银行MT41J128M8 â ????梅格16 ×8× 8银行MT41J64M16 â ???? 8梅格×16× 8银行 [DDR3 SDRAM MT41J256M4 – 32 Meg x 4 x 8 banks MT41J128M8 – 16 Meg x 8 x 8 banks MT41J64M16 – 8 Meg x 16 x 8 banks]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 214 页 / 2938 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号MT41J256M4的Datasheet PDF文件第75页浏览型号MT41J256M4的Datasheet PDF文件第76页浏览型号MT41J256M4的Datasheet PDF文件第77页浏览型号MT41J256M4的Datasheet PDF文件第78页浏览型号MT41J256M4的Datasheet PDF文件第80页浏览型号MT41J256M4的Datasheet PDF文件第81页浏览型号MT41J256M4的Datasheet PDF文件第82页浏览型号MT41J256M4的Datasheet PDF文件第83页  
Electrical Characteristics and AC Operating Conditions  
Table 56: Electrical Characteristics and AC Operating Conditions  
Notes 1–8 apply to the entire table  
DDR3-800  
DDR3-1066  
DDR3-1333  
DDR3-1600  
Parameter  
Symbol  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Unit Notes  
Clock Timing  
Clock period average:  
DLL disable mode  
TC 85°C  
tCK  
(DLL_DIS)  
8
8
7800  
3900  
8
7800  
3900  
8
8
7800  
3900  
8
8
7800  
3900  
ns  
ns  
ns  
CK  
CK  
ps  
ps  
ps  
9, 42  
42  
TC = >85°C to 95°C  
8
Clock period average: DLL enable mode  
High pulse width average  
tCK (AVG)  
tCH (AVG)  
tCL (AVG)  
tJITper  
tJITper,lck  
tCK (ABS)  
See Speed Bin Tables (page 74) for tCK range allowed  
10, 11  
12  
0.47  
0.47  
–100  
–90  
0.53  
0.53  
100  
90  
0.47  
0.47  
–90  
0.53  
0.53  
90  
0.47  
0.47  
–80  
0.53  
0.53  
80  
0.47  
0.47  
–70  
0.53  
0.53  
70  
Low pulse width average  
12  
Clock period jitter  
DLL locked  
DLL locking  
13  
–80  
80  
–70  
70  
–60  
60  
13  
Clock absolute period  
MIN = tCK (AVG) MIN + tJITper MIN; MAX = tCK (AVG) MAX + tJITper  
MAX  
Clock absolute high pulse width  
Clock absolute low pulse width  
tCH (ABS)  
tCL (ABS)  
0.43  
0.43  
0.43  
0.43  
tCK  
(AVG)  
tCK  
14  
15  
0.43  
0.43  
0.43  
0.43  
(AVG)  
Cycle-to-cycle jitter  
DLL locked  
DLL locking  
tJITcc  
200  
180  
180  
160  
160  
140  
140  
120  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
16  
16  
17  
17  
17  
17  
17  
17  
17  
17  
17  
17  
17  
17  
tJITcc,lck  
tERR2per  
tERR3per  
tERR4per  
tERR5per  
tERR6per  
tERR7per  
tERR8per  
tERR9per  
tERR10per  
tERR11per  
tERR12per  
Cumulative error across 2 cycles  
–147  
–175  
–194  
–209  
–222  
–232  
–241  
–249  
–257  
–263  
–269  
147  
175  
194  
209  
222  
232  
241  
249  
257  
263  
269  
–132  
–157  
–175  
–188  
–200  
–209  
–217  
–224  
–231  
–237  
–242  
132  
157  
175  
188  
200  
209  
217  
224  
231  
237  
242  
–118  
–140  
–155  
–168  
–177  
–186  
–193  
–200  
–205  
–210  
–215  
118  
140  
155  
168  
177  
186  
193  
200  
205  
210  
215  
–103  
–122  
–136  
–147  
–155  
–163  
–169  
–175  
–180  
–184  
–188  
103  
122  
136  
147  
155  
163  
169  
175  
180  
184  
188  
3 cycles  
4 cycles  
5 cycles  
6 cycles  
7 cycles  
8 cycles  
9 cycles  
10 cycles  
11 cycles  
12 cycles  
n = 13, 14 . . . 49, 50 tERRnper  
tERRnper MIN = (1 + 0.68ln[n]) × tJITper MIN  
cycles  
tERRnper MAX = (1 + 0.68ln[n]) × tJITper MAX  
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